公开(公告)号：US11742293B2

公开(公告)日：2023-08-29

申请号：US16480654

申请日：2017-03-22

Applicant: Intel Corporation

Inventor： Yidnekachew S. Mekonnen ,  Kemel Aygun ,  Ravindranath V. Mahajan ,  Christopher S. Baldwin ,  Rajasekaran Swaminathan

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/14 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L21/4853 ,  H01L23/145 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16235

Abstract: A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.

公开(公告)号：US09418906B2

公开(公告)日：2016-08-16

申请号：US14816611

申请日：2015-08-03

Applicant: Intel Corporation

Inventor： Mark B. Trobough ,  Christopher S. Baldwin

IPC: H01L21/00 ,  H01L21/66 ,  G01R1/04 ,  H01L23/498

CPC classification number: H01L22/14 ,  G01R1/0483 ,  H01L22/32 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.

公开(公告)号：US20150340295A1

公开(公告)日：2015-11-26

申请号：US14816611

申请日：2015-08-03

Applicant: Intel Corporation

Inventor： Mark B. Trobough ,  Christopher S. Baldwin

IPC: H01L21/66

CPC classification number: H01L22/14 ,  G01R1/0483 ,  H01L22/32 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，集成电路封装包括多个系统功能引脚，至少一个系统功能引脚释放区，以及至少一个非系统功能引脚，位于该至少一个功能引脚销毁区中。 描述和要求保护其他实施例。