公开(公告)号：US20160170923A1

公开(公告)日：2016-06-16

申请号：US14566468

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： Patrick G. Kutch ,  Daniel P. Daly

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4282

Abstract: Apparatuses, methods and storage media associated with the exchange of messages between a hybrid switch and one or more baseboard management controllers (BMCs) are described herein. Specifically, an aggregate BMC controller (ABC) may be communicatively coupled with both the hybrid switch and the BMCs and configured to facilitate the exchange of messages between the hybrid switch and the one or more BMCs. Other embodiments may be described and/or claimed.

Abstract translation: 这里描述了与混合交换机和一个或多个基板管理控制器（BMC）之间的消息交换相关联的装置，方法和存储介质。 具体地，聚合BMC控制器（ABC）可以与混合交换机和BMC通信耦合，并且被配置为便于混合交换机与一个或多个BMC之间的消息交换。 可以描述和/或要求保护其他实施例。

公开(公告)号：US11750533B2

公开(公告)日：2023-09-05

申请号：US16643626

申请日：2017-10-24

Applicant: Intel Corporation

Inventor： Daniel P. Daly ,  Cunming Liang ,  Jian Wang ,  Martin Roberts ,  Shih-Wei Chien ,  Gerald Alan Rogers

IPC: H04L49/00 ,  G06F12/0868 ,  H04L15/16 ,  G06F12/06 ,  G06F12/12 ,  H04L12/931 ,  H04L12/861 ,  G06F12/10 ,  H04L49/90

CPC classification number: H04L49/70 ,  G06F12/0868 ,  G06F12/10 ,  G06F12/12 ,  H04L49/90 ,  G06F2212/152 ,  G06F2212/154

Abstract: There is disclosed an example of a computing apparatus for providing a hardware-assisted virtual switch on a host, including: a hardware virtual switch (vSwitch) circuit; and a hardware virtual host (vHost) circuit, the vHost circuit having an interface driver specific to the hardware vSwitch and configured to provide a vHost data plane to: provide a plurality of hardware queues to communicatively couple the hardware vSwitch to a guest virtual function (VF); and present to a virtual network driver of the guest VF an interface that is backward compatible with a software network interface.

公开(公告)号：US20230115114A1

公开(公告)日：2023-04-13

申请号：US18078382

申请日：2022-12-09

Applicant: Intel Corporation

Inventor： Daniel P. Daly ,  Cunming Liang ,  Jian Wang ,  Martin Roberts ,  Shih-Wei Chien ,  Gerald Alan Rogers

IPC: H04L49/00 ,  G06F12/0868 ,  G06F12/10 ,  G06F12/12 ,  H04L49/90

Abstract: There is disclosed an example of a computing apparatus for providing a hardware-assisted virtual switch on a host, including: a hardware virtual switch (vSwitch) circuit; and a hardware virtual host (vHost) circuit, the vHost circuit having an interface driver specific to the hardware vSwitch and configured to provide a vHost data plane to: provide a plurality of hardware queues to communicatively couple the hardware vSwitch to a guest virtual function (VF); and present to a virtual network driver of the guest VF an interface that is backward compatible with a software network interface.

公开(公告)号：US20210141676A1

公开(公告)日：2021-05-13

申请号：US17152573

申请日：2021-01-19

Applicant: Intel Corporation

Inventor： Ren Wang ,  Daniel P. Daly ,  Antoine Kaufmann ,  Saikrishna Edupuganti ,  Tsung-Yuan C. Tai

IPC: G06F9/50

Abstract: A network interface card (NIC) can be configured to monitor a first central processing unit (CPU) core mapped to a first receive queue having a receive queue length. The NIC can also be configured to determine whether the CPU core is overloaded based on the receive queue length. The NIC can also be configured to redirect data packets that were targeted from the first receive queue to the CPU core to another CPU core responsive to a determination that the CPU core is overloaded.

公开(公告)号：US10268464B2

公开(公告)日：2019-04-23

申请号：US15644150

申请日：2017-07-07

Applicant: Intel Corporation

Inventor： Daniel P. Daly ,  Thomas E. Willis ,  Pat Wang ,  Vishal Anand ,  Hung Nguyen ,  Varsha Apte

IPC: G06F8/41 ,  G06F8/51 ,  G11C15/04 ,  G11C11/412

Abstract: Technologies for network application programming include a computing device that analyzes a network application source program. The source program includes a declarative description of a network application in a domain-specific language, such as P4. The computing device translates the declarative description of the network application into a register-transfer level (RTL) description, and then compiles the RTL description into a bitstream definition that is targeted to an FPGA. For example, the computing device may generate a parse graph based on the network application source program, and then generate an RTL TCAM-SRAM structure for each node of the parse graph. The computing device may optimize the RTL description, for example by simplifying RTL structures or removing unused logic. The computing device may program an FPGA with the bitstream definition. Other embodiments are described and claimed.

公开(公告)号：US09898435B2

公开(公告)日：2018-02-20

申请号：US14566468

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： Patrick G. Kutch ,  Daniel P. Daly

IPC: G06F13/20 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4282

Abstract: Apparatuses, methods and storage media associated with the exchange of messages between a hybrid switch and one or more baseboard management controllers (BMCs) are described herein. Specifically, an aggregate BMC controller (ABC) may be communicatively coupled with both the hybrid switch and the BMCs and configured to facilitate the exchange of messages between the hybrid switch and the one or more BMCs. Other embodiments may be described and/or claimed.

公开(公告)号：US20190012156A1

公开(公告)日：2019-01-10

申请号：US15644150

申请日：2017-07-07

Applicant: Intel Corporation

Inventor： Daniel P. Daly ,  Thomas E. Willis ,  Pat Wang ,  Vishal Anand ,  Hung Nguyen ,  Varsha Apte

IPC: G06F9/45

Abstract: Technologies for network application programming include a computing device that analyzes a network application source program. The source program includes a declarative description of a network application in a domain-specific language, such as P4. The computing device translates the declarative description of the network application into a register-transfer level (RTL) description, and then compiles the RTL description into a bitstream definition that is targeted to an FPGA. For example, the computing device may generate a parse graph based on the network application source program, and then generate an RTL TCAM-SRAM structure for each node of the parse graph. The computing device may optimize the RTL description, for example by simplifying RTL structures or removing unused logic. The computing device may program an FPGA with the bitstream definition. Other embodiments are described and claimed.

公开(公告)号：US20180285151A1

公开(公告)日：2018-10-04

申请号：US15476379

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ren Wang ,  Daniel P. Daly ,  Antoine Kaufmann ,  Saikrishna Edupuganti ,  Tsung-Yuan C. Tai

IPC: G06F9/48 ,  G06F11/34 ,  G06F11/30

Abstract: A network interface card (NIC) can be configured to monitor a first central processing unit (CPU) core mapped to a first receive queue having a receive queue length. The NIC can also be configured to determine whether the CPU core is overloaded based on the receive queue length. The NIC can also be configured to redirect data packets that were targeted from the first receive queue to the CPU core to another CPU core responsive to a determination that the CPU core is overloaded.

公开(公告)号：US09904027B2

公开(公告)日：2018-02-27

申请号：US15378786

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Donald L. Faw ,  Uri V. Cummings ,  Terrence J. Trausch ,  Daniel P. Daly ,  Andrew C. Alduino

IPC: G02B6/00 ,  G02B6/44 ,  H05K7/14 ,  G02B6/38 ,  H04Q1/02

CPC classification number: G02B6/4452 ,  G02B6/3897 ,  G06F1/183 ,  H04Q1/09 ,  H04Q1/13 ,  H05K7/1487 ,  H05K7/1489 ,  H05K7/1492 ,  Y10T29/49906

Abstract: Embodiments of the present disclosure provide techniques and configurations for a rack assembly. In one embodiment, a tray to be disposed in a rack assembly may comprise a plurality of sleds with individual sleds including one or more compute nodes; and a networking element coupled with a sled of the plurality of sleds and configured to communicatively connect the sled to one or more other components of the rack assembly via an optical communication system. The optical communication system may include an external optical cable configured to communicatively connect the networking element with the rack assembly. Other embodiments may be described and/or claimed.