公开(公告)号：US20210216377A1

公开(公告)日：2021-07-15

申请号：US17213747

申请日：2021-03-26

申请人： Intel Corporation

发明人： Niharika Arlagadda Narasimharaju ,  Sudheer Nair ,  James Hermerding, II ,  Merwin Brown ,  Deepak Ganapathy ,  Fabian Garita Gonzalez

IPC分类号： G06F9/50 ,  G06F1/28

摘要： Methods, apparatus, systems and articles of manufacture for power sharing between discrete processors are disclosed. An example apparatus includes a thermal monitor to monitor temperatures of first and second discrete processors and a balance controller to, in response to a first temperature of the first processor satisfying a temperature threshold, adjust first and second power budgets allocated to the respective first and second processors.

公开(公告)号：US20240241559A1

公开(公告)日：2024-07-18

申请号：US18619538

申请日：2024-03-28

申请人： Intel Corporation

发明人： Rob Sims ,  Deepak Ganapathy ,  Sivasankara Reddy Juturu ,  Sudheer Nair

IPC分类号： G06F1/28 ,  G06F1/3206

CPC分类号： G06F1/28 ,  G06F1/3206

摘要： Techniques are described for incorporating telemetry related to power source loading and the frequency of power-control events as part of a power balancing algorithm to control an electronic devices' power budgeting among devices sharing a common power source. The techniques utilize telemetry and control loop algorithms to dynamically balance the power between two or more electronic components, which may include a CPU and a GPU. The techniques as described herein function to monitor power source loading as well as the frequency of a predetermined set of events, which may include performance and/or power control events. Based on this information, the power budgets of the devices may be dynamically adjusted up or down to maximize performance, in contrast with the conventional usage of artificial static performance caps.

公开(公告)号：US20220326096A1

公开(公告)日：2022-10-13

申请号：US17850561

申请日：2022-06-27

申请人： Intel Corporation

发明人： Smit Kapila ,  Abhishek Srivastav ,  Sumod Cherukkate ,  Manit Biswas ,  Zhongsheng Wang ,  Bijendra Singh ,  Deepak Ganapathy ,  Dipen Dudhat

IPC分类号： G01K11/22 ,  H05K7/20

摘要： Methods, apparatus, systems, and articles of manufacture are disclosed to monitor thermal degradation of a compute device. One such method includes calculating, by executing instructions with processor circuitry, a thermal degradation value based on an equation, the equation generated based on testing of thermal interface materials having varying degrees of degradation. The method also includes comparing, by executing instructions with the processor circuitry, the thermal degradation value to a thermal degradation threshold to determine whether the thermal degradation threshold is satisfied, and, when the thermal degradation threshold is satisfied, triggering generation of a thermal degradation alert.

公开(公告)号：US11016916B2

公开(公告)日：2021-05-25

申请号：US16868603

申请日：2020-05-07

申请人： Intel Corporation

发明人： Xiuting C. Man ,  Jeremy J. Shrall ,  Deepak Ganapathy ,  Dorit Shapira

IPC分类号： G06F13/24 ,  G06F1/3296 ,  G06F1/20 ,  G06F1/3234

摘要： In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.

公开(公告)号：US10657083B2

公开(公告)日：2020-05-19

申请号：US15281472

申请日：2016-09-30

申请人： Intel Corporation

发明人： Xiuting C. Man ,  Jeremy J. Shrall ,  Deepak Ganapathy ,  Dorit Shapira

IPC分类号： G06F13/12 ,  G06F13/24 ,  G06F1/3296 ,  G06F1/20 ,  G06F1/3234

摘要： In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.