公开(公告)号：US20210375719A1

公开(公告)日：2021-12-02

申请号：US17399882

申请日：2021-08-11

Applicant: Intel Corporation

Inventor： Feras Eid ,  Shrenik Kothari ,  Chandra M. Jha ,  Johanna M. Swan ,  Michael J. Baker ,  Shawna M. Liff ,  Thomas L. Sounart ,  Betsegaw K. Gebrehiwot ,  Shankar Devasenathipathy ,  Taylor Gaines ,  Digvijay Ashokkumar Raorane

IPC: H01L23/433 ,  H01L23/29 ,  H01L21/56 ,  H01L25/00 ,  H01L25/18 ,  H01L23/42 ,  H01L23/367 ,  H01L23/04 ,  H01L25/065 ,  H01L25/16 ,  H01L23/16

Abstract: A semiconductor device that has a semiconductor die coupled to a substrate. A mold compound encapsulates the semiconductor die, and at least one thermal conductive material section extends from adjacent the semiconductor die through the mold compound. The at least one conductive material section thus conveys heat from the semiconductor die through the mold compound.

公开(公告)号：US20200211966A1

公开(公告)日：2020-07-02

申请号：US16236016

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Digvijay Ashokkumar Raorane

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/15 ,  H01L25/065 ,  H01L23/367 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: Ceramic interposers in a disaggregated-die semiconductor package allow for useful signal integrity and interconnecting components. Low-loss ceramics are used to tune ceramic interposers for a die assembly that may have components from different process-technology nodes.

公开(公告)号：US11594493B2

公开(公告)日：2023-02-28

申请号：US16921469

申请日：2020-07-06

Applicant: Intel Corporation

Inventor： Digvijay Ashokkumar Raorane

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/15 ,  H01L25/065 ,  H01L23/367 ,  H01L25/00 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: Ceramic interposers in a disaggregated-die semiconductor package allow for useful signal integrity and interconnecting components. Low-loss ceramics are used to tune ceramic interposers for a die assembly that may have components from different process-technology nodes.

公开(公告)号：US10707169B1

公开(公告)日：2020-07-07

申请号：US16236016

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Digvijay Ashokkumar Raorane

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/15 ,  H01L25/065 ,  H01L23/367 ,  H01L25/00 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: Ceramic interposers in a disaggregated-die semiconductor package allow for useful signal integrity and interconnecting components. Low-loss ceramics are used to tune ceramic interposers for a die assembly that may have components from different process-technology nodes.

公开(公告)号：US20190304809A1

公开(公告)日：2019-10-03

申请号：US15937453

申请日：2018-03-27

Applicant: Intel Corporation

Inventor： Digvijay Ashokkumar Raorane ,  Ravindranath V. Mahajan

IPC: H01L21/56 ,  H01L21/683 ,  H01L21/68 ,  H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538

Abstract: A method of aligning semiconductor dies having metallic bumps in a mold chase for further processing. A plurality of semiconductor dies are placed in the mold chase at approximately desired locations for further processing. A plurality of magnets in a retainer are associated with the mold chase, the plurality of magnets being associated with respective ones of the plurality of semiconductor dies. The magnetic field of the magnets is applied to align and hold the plurality of dies at the desired location. The plurality of magnets may be adjustably mounted in the retainer so that they can be adjusted to more precisely align the semiconductor dies at the desired locations.

公开(公告)号：US20210391638A1

公开(公告)日：2021-12-16

申请号：US17458911

申请日：2021-08-27

Applicant: Intel Corporation

Inventor： Vijay K. Nair ,  Digvijay Ashokkumar Raorane

IPC: H01Q1/22 ,  H01L21/48 ,  H01L23/13 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01L25/065 ,  H01Q13/00

Abstract: Generally discussed herein are systems, devices, and methods that include a communication cavity. According to an example a device can include substrate with a first cavity formed therein, first and second antennas exposed in and enclosed by the cavity, and an interconnect structure formed in the substrate, the interconnect structure including alternating conductive material layers and inter-layer dielectric layers.

公开(公告)号：US11978948B2

公开(公告)日：2024-05-07

申请号：US17458911

申请日：2021-08-27

Applicant: Intel Corporation

Inventor： Vijay K. Nair ,  Digvijay Ashokkumar Raorane

IPC: H01Q1/22 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H01Q13/00

CPC classification number: H01Q1/2283 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/16 ,  H01L25/0655 ,  H01Q13/00 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237

Abstract: Generally discussed herein are systems, devices, and methods that include a communication cavity. According to an example a device can include substrate with a first cavity formed therein, first and second antennas exposed in and enclosed by the cavity, and an interconnect structure formed in the substrate, the interconnect structure including alternating conductive material layers and inter-layer dielectric layers.

公开(公告)号：US11195806B2

公开(公告)日：2021-12-07

申请号：US16348698

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Vijay K. Nair ,  Digvijay Ashokkumar Raorane

IPC: H01L23/66 ,  H01L23/48 ,  H01L23/538 ,  H01P3/12 ,  H01P11/00 ,  H04B7/00 ,  H01L25/065

Abstract: An integrated circuit (IC) comprises a substrate, a first die mounted on the substrate, a second die mounted on the substrate and a waveguide structure mounted on the first die and the second die to enable high frequency wireless communication between the first die and the second die.

公开(公告)号：US20210028117A1

公开(公告)日：2021-01-28

申请号：US16921469

申请日：2020-07-06

Applicant: Intel Corporation

Inventor： Digvijay Ashokkumar Raorane

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/15 ,  H01L25/065 ,  H01L23/367 ,  H01L25/00 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: Ceramic interposers in a disaggregated-die semiconductor package allow for useful signal integrity and interconnecting components. Low-loss ceramics are used to tune ceramic interposers for a die assembly that may have components from different process-technology nodes.

公开(公告)号：US10804117B2

公开(公告)日：2020-10-13

申请号：US15937453

申请日：2018-03-27

Applicant: Intel Corporation

Inventor： Digvijay Ashokkumar Raorane ,  Ravindranath V. Mahajan

IPC: H01L21/56 ,  H01L21/683 ,  H01L21/68 ,  H01L21/66 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: A method of aligning semiconductor dies having metallic bumps in a mold chase for further processing. A plurality of semiconductor dies are placed in the mold chase at approximately desired locations for further processing. A plurality of magnets in a retainer are associated with the mold chase, the plurality of magnets being associated with respective ones of the plurality of semiconductor dies. The magnetic field of the magnets is applied to align and hold the plurality of dies at the desired location. The plurality of magnets may be adjustably mounted in the retainer so that they can be adjusted to more precisely align the semiconductor dies at the desired locations.