公开(公告)号：US20230305982A1

公开(公告)日：2023-09-28

申请号：US18327043

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jakob Raymond Jones

IPC: H01L25/065 ,  H01L23/00 ,  G06F13/42 ,  G06F13/38 ,  G06F13/40 ,  H03K19/173 ,  H01L23/498

CPC classification number: G06F13/4045 ,  G06F13/385 ,  G06F13/42 ,  G06F13/4291 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H03K19/1736 ,  H01L2224/16225 ,  H01L2924/1431 ,  H04W56/0015

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

公开(公告)号：US11100029B2

公开(公告)日：2021-08-24

申请号：US16536147

申请日：2019-08-08

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jakob Raymond Jones

IPC: G06F13/40 ,  G06F13/38 ,  H01L23/52 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  G06F13/42 ,  H03K19/173 ,  H04W56/00

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

公开(公告)号：US10445278B2

公开(公告)日：2019-10-15

申请号：US15392225

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jakob Raymond Jones

IPC: G06F13/40 ,  G06F13/38 ,  H01L23/52 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  G06F13/42 ,  H03K19/173 ,  H04W56/00

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

公开(公告)号：US20220121595A1

公开(公告)日：2022-04-21

申请号：US17561918

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jakob Raymond Jones

IPC: G06F13/40 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  G06F13/42 ,  G06F13/38 ,  H03K19/173

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

公开(公告)号：US11237998B2

公开(公告)日：2022-02-01

申请号：US17131404

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jakob Raymond Jones

IPC: H01L25/065 ,  G06F13/40 ,  G06F13/42 ,  H01L23/498 ,  H01L23/00 ,  G06F13/38 ,  H03K19/173 ,  H04W56/00

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

公开(公告)号：US20180181524A1

公开(公告)日：2018-06-28

申请号：US15392225

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jakob Raymond Jones

IPC: G06F13/40 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  G06F13/42

CPC classification number: G06F13/4045 ,  G06F13/385 ,  G06F13/42 ,  G06F13/4291 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/1431 ,  H03K19/1736 ,  H04W56/0015

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

公开(公告)号：US12135667B2

公开(公告)日：2024-11-05

申请号：US18327043

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jakob Raymond Jones

IPC: H01L25/065 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  H01L23/00 ,  H01L23/498 ,  H03K19/173 ,  H04W56/00

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

公开(公告)号：US11693810B2

公开(公告)日：2023-07-04

申请号：US17561918

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jakob Raymond Jones

IPC: H01L25/065 ,  G06F13/40 ,  G06F13/42 ,  H01L23/498 ,  H01L23/00 ,  G06F13/38 ,  H03K19/173 ,  H04W56/00

CPC classification number: G06F13/4045 ,  G06F13/385 ,  G06F13/42 ,  G06F13/4291 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H03K19/1736 ,  H01L2224/16225 ,  H01L2924/1431 ,  H04W56/0015

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

公开(公告)号：US20210109883A1

公开(公告)日：2021-04-15

申请号：US17131404

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jacob Raymond Jones

IPC: G06F13/40 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  G06F13/42 ,  G06F13/38 ,  H03K19/173

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.