公开(公告)号：US12191893B2

公开(公告)日：2025-01-07

申请号：US17385556

申请日：2021-07-26

Applicant: Intel Corporation

Inventor： David W. Mendel ,  Jeffrey Erik Schulz ,  Keith Duwel ,  Huy Ngo ,  Jakob Raymond Jones

IPC: H03M9/00 ,  G06F1/12 ,  G06F13/42 ,  H03K19/17736

Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.

公开(公告)号：US20200028521A1

公开(公告)日：2020-01-23

申请号：US16585934

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： David W. Mendel ,  Jeffrey Erik Schulz ,  Keith Duwel ,  Huy Ngo ,  Jakob Raymond Jones

IPC: H03M9/00 ,  G06F1/12 ,  H03K19/177 ,  G06F13/42

Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.

公开(公告)号：US10439639B2

公开(公告)日：2019-10-08

申请号：US15392209

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： David W. Mendel ,  Jeffrey Erik Schulz ,  Keith Duwel ,  Huy Ngo ,  Jakob Raymond Jones

IPC: H03M9/00 ,  G06F1/12 ,  G06F13/42 ,  H03K19/177

Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.

公开(公告)号：US11449247B2

公开(公告)日：2022-09-20

申请号：US16953138

申请日：2020-11-19

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Curtis Wortman ,  Jeffrey Erik Schulz

IPC: G06F3/06 ,  G06F13/38 ,  G11C7/10

Abstract: A multichip package may include at least a main die mounted on a substrate. The main die may be coupled to one or more transceiver dies also mounted on the substrate. The main die may include one or more universal interface blocks configured to interface with an on-package memory device or an on-package expansion die, both of which can be mounted on the substrate. The expansion die may include external memory interface (EMIF) components for communicating with off-package memory devices and/or bulk random-access memory (RAM) components for storing large amounts of data for the main die. Smaller input-output blocks such as GPIO (general purpose input-output) or LVDS (low-voltage differential signaling) interfaces may be formed within the core fabric of the main die without causing routing congestion while providing the necessary clock source.

公开(公告)号：US10445278B2

公开(公告)日：2019-10-15

申请号：US15392225

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jakob Raymond Jones

IPC: G06F13/40 ,  G06F13/38 ,  H01L23/52 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  G06F13/42 ,  H03K19/173 ,  H04W56/00

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

公开(公告)号：US20180183463A1

公开(公告)日：2018-06-28

申请号：US15392209

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： David W. Mendel ,  Jeffrey Erik Schulz ,  Keith Duwel ,  Huy Ngo ,  Jakob Raymond Jones

IPC: H03M9/00 ,  G06F1/12

CPC classification number: H03M9/00 ,  G06F1/12 ,  G06F13/4282 ,  H03K19/17744

Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.

公开(公告)号：US20230305982A1

公开(公告)日：2023-09-28

申请号：US18327043

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jakob Raymond Jones

IPC: H01L25/065 ,  H01L23/00 ,  G06F13/42 ,  G06F13/38 ,  G06F13/40 ,  H03K19/173 ,  H01L23/498

CPC classification number: G06F13/4045 ,  G06F13/385 ,  G06F13/42 ,  G06F13/4291 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H03K19/1736 ,  H01L2224/16225 ,  H01L2924/1431 ,  H04W56/0015

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

公开(公告)号：US20220190843A1

公开(公告)日：2022-06-16

申请号：US17385556

申请日：2021-07-26

Applicant: Intel Corporation

Inventor： David W. Mendel ,  Jeffrey Erik Schulz ,  Keith Duwel ,  Huy Ngo ,  Jakob Raymond Jones

IPC: H03M9/00 ,  G06F1/12 ,  G06F13/42 ,  H03K19/17736

Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.

公开(公告)号：US11100029B2

公开(公告)日：2021-08-24

申请号：US16536147

申请日：2019-08-08

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jakob Raymond Jones

IPC: G06F13/40 ,  G06F13/38 ,  H01L23/52 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  G06F13/42 ,  H03K19/173 ,  H04W56/00

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

公开(公告)号：US20210072908A1

公开(公告)日：2021-03-11

申请号：US16953138

申请日：2020-11-19

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Curtis Wortman ,  Jeffrey Erik Schulz

IPC: G06F3/06 ,  G11C7/10 ,  G06F13/38

Abstract: A multichip package may include at least a main die mounted on a substrate. The main die may be coupled to one or more transceiver dies also mounted on the substrate. The main die may include one or more universal interface blocks configured to interface with an on-package memory device or an on-package expansion die, both of which can be mounted on the substrate. The expansion die may include external memory interface (EMIF) components for communicating with off-package memory devices and/or bulk random-access memory (RAM) components for storing large amounts of data for the main die. Smaller input-output blocks such as GPIO (general purpose input-output) or LVDS (low-voltage differential signaling) interfaces may be formed within the core fabric of the main die without causing routing congestion while providing the necessary clock source.