Seemingly monolithic interface between separate integrated circuit die

    公开(公告)号:US12191893B2

    公开(公告)日:2025-01-07

    申请号:US17385556

    申请日:2021-07-26

    Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.

    SEEMINGLY MONOLITHIC INTERFACE BETWEEN SEPARATE INTEGRATED CIRCUIT DIE

    公开(公告)号:US20200028521A1

    公开(公告)日:2020-01-23

    申请号:US16585934

    申请日:2019-09-27

    Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.

    Seemingly monolithic interface between separate integrated circuit die

    公开(公告)号:US10439639B2

    公开(公告)日:2019-10-08

    申请号:US15392209

    申请日:2016-12-28

    Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.

    SEEMINGLY MONOLITHIC INTERFACE BETWEEN SEPARATE INTEGRATED CIRCUIT DIE

    公开(公告)号:US20220190843A1

    公开(公告)日:2022-06-16

    申请号:US17385556

    申请日:2021-07-26

    Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.

    SEEMINGLY MONOLITHIC INTERFACE BETWEEN SEPARATE INTEGRATED CIRCUIT DIE

    公开(公告)号:US20180183463A1

    公开(公告)日:2018-06-28

    申请号:US15392209

    申请日:2016-12-28

    CPC classification number: H03M9/00 G06F1/12 G06F13/4282 H03K19/17744

    Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.

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