公开(公告)号：US20180253355A1

公开(公告)日：2018-09-06

申请号：US15909929

申请日：2018-03-01

Applicant: Intel Corporation

Inventor： Kiran PANGAL ,  Prashant S. DAMLE ,  Rajesh SUNDARAM ,  Shekoufeh QAWAMI ,  Julie M. WALKER ,  Doyle RIVERS

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/27 ,  H03M13/05 ,  G06F3/06 ,  H03M13/15 ,  H03M13/19

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  H03M13/05 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/27 ,  H03M13/6508

Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.