公开(公告)号：US12111775B2

公开(公告)日：2024-10-08

申请号：US17212722

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Duane E. Galbi ,  Matthew J. Adiletta ,  Hugh Wilkinson ,  Patrick Connor

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1621 ,  G06F13/1668 ,  G06F13/409 ,  G06F13/4221

Abstract: Examples described herein relate to an apparatus that includes at least two processing units and a memory hub coupled to the at least two processing units. In some examples, the memory hub includes a home agent. In some examples, the memory hub is to perform a memory access request involving a memory device, a first processing unit among the at least two processing units is to send the memory access request to the memory hub. In some examples, the first processing unit is to offload at least some but not all home agent operations to the home agent of the memory hub. In some examples, the first processing unit comprises a second home agent and wherein the second home agent is to perform the at least some but not all home agent operations before the offload of at least some but not all home agent operations to the home agent of the memory hub. In some examples, based on provision of the at least some but not all home agent operations to be performed by the second home agent, the second home agent is to perform the at least some but not all home agent operations.

公开(公告)号：US12099408B2

公开(公告)日：2024-09-24

申请号：US17132982

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Duane E. Galbi ,  Matthew J. Adiletta

IPC: G06F11/10 ,  G06F11/07 ,  G06F12/0879

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0772 ,  G06F12/0879

Abstract: An apparatus is described. The apparatus includes a memory controller having logic circuitry to write a unit of write data into a plurality of memory chips according to a striping pattern that includes multiple protected sub words, each protected sub word including a smaller portion of the unit of write data and error correction coding (ECC) information calculated from the smaller portion of the unit of write data.

公开(公告)号：US11699471B2

公开(公告)日：2023-07-11

申请号：US17030107

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Duane E. Galbi ,  Bill Nale

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/16 ,  G06F13/28 ,  G11C8/18

CPC classification number: G11C7/222 ,  G06F13/1684 ,  G06F13/287 ,  G11C7/1012 ,  G11C8/18

Abstract: An apparatus is described. The apparatus includes logic circuitry to multiplex on a data bus a first data burst, a second data burst, a third data burst and a fourth data burst having different respective base target addresses that respectively target a first memory rank, a second memory rank, a third memory rank and a fourth memory rank. A first data transfer for the first data burst occurs on a first edge of a first pulse of a data strobe signal for the data bus and a second data transfer for the second data burst occurs on a second edge of the first pulse of the data strobe signal. A third data transfer for the third data burst occurs on a first edge of a second pulse of the data strobe signal for the data bus and a fourth data transfer for the fourth data burst occurs on a second edge of the second pulse. The second pulse immediately follows the first pulse on the data strobe signal. The first memory rank, the second memory rank, the third memory rank and the fourth memory rank are on a same memory module.