Device and method for determining a model related to a temperature shift

    公开(公告)号:US11592339B2

    公开(公告)日:2023-02-28

    申请号:US16727966

    申请日:2019-12-27

    Abstract: A device may comprise: a storage for storing a reference output representing an output of an electrical circuit at a reference temperature; one or more processors, configured to: determine a temperature shift based on a comparison of an output of the electrical circuit sensed at a sensing temperature and the reference output; determine a plurality of coefficients of a model of the temperature shift, wherein the model implements one or more functions that associate the plurality of coefficients and a temperature with the temperature shift at the temperature.

    APPARATUS, SYSTEM AND METHOD OF PHASE SHIFTING

    公开(公告)号:US20240113696A1

    公开(公告)日:2024-04-04

    申请号:US17958340

    申请日:2022-10-01

    CPC classification number: H03H11/16 G06F1/08 H04L27/2067

    Abstract: For example, a phase shifter may include an input to receive an input clock signal having an input frequency and an input phase. For example, the phase shifter may include a quadrature phase-shift generator configured to generate a first signal and a second signal based on the input clock signal, the first and second signals having the input frequency, wherein a phase of the first signal is based on the input phase, wherein a phase of the second signal is shifted by a quadrature phase-shift relative to the phase of the first signal. For example, the phase shifter may include an output to provide an output based on the first signal and the second signal.

    MULTI-CORE DIGITAL POWER AMPLIFIER WITH UNBALANCED COMBINER

    公开(公告)号:US20220416736A1

    公开(公告)日:2022-12-29

    申请号:US17359187

    申请日:2021-06-25

    Abstract: Various embodiments provide systems, devices, and methods for a multi-core digital power amplifier with an unbalanced power combiner. In one example, two or more cores are combined with a transformer section that has a first coupling coefficient and another two or more cores are combined with a second transformer section that has a second coupling coefficient that is different than the first coupling coefficient. The outputs of different cores may be cross-coupled with the primary inductors of the transformers. The digital power amplifier may provide an output power that is flat over a relatively wide operating range. Other embodiments may be described and claimed.

    Closed loop transmitter (Tx) calibration with frequency separation using a digital to time converter (DTC)

    公开(公告)号:US10931384B1

    公开(公告)日:2021-02-23

    申请号:US16727512

    申请日:2019-12-26

    Abstract: A closed loop transmitter (Tx) calibration system is disclosed. The closed loop Tx calibration system comprises a transmitter circuit configured to generate a Tx output signal at a Tx output frequency based on a Tx local oscillator (LO) signal. The closed loop Tx calibration system further comprises a loop back (LPBK) receiver circuit coupled to the transmitter circuit and configured to downconvert the Tx output signal at the Tx output frequency to form an LPBK baseband signal at an LPBK intermediate frequency (IF), based on an LPBK LO signal. In some embodiments, the LPBK IF frequency is different from zero. In some embodiments, the closed loop Tx calibration system further comprises an LO generation circuit configured to generate the Tx LO signal and the LPBK LO signal from a single phase locked loop (PLL) source, based on utilizing a digital to time converter (DTC) circuit.

    Binary stochastic time-to-digital converter and method

    公开(公告)号:US09927775B1

    公开(公告)日:2018-03-27

    申请号:US15477057

    申请日:2017-04-01

    CPC classification number: G04F10/005 H03K19/23

    Abstract: A method and apparatus for determining a difference between signal edges in two signals includes a multiple stage converter where each stage determines which of the two signals has an earlier signal edge, outputs a value corresponding to that determination, and then applies a delay to the earlier signal that is equal to half of the delay applied by the next previous stage. The stages examine smaller and smaller intervals to the sought-after signal edge. Each stage includes a plurality of logic elements. If all logic elements in the stage output the same signal, the edge position is clear. If some of the logic elements in the stage vote differently than others in the state due to differences in setup time for the different elements, the edge location has been found within the sensing band of the stage.

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