-
公开(公告)号：US20240113670A1
公开(公告)日：2024-04-04
申请号：US17957011
申请日：2022-09-30
Applicant: INTEL CORPORATION
Inventor： Ofir Degani , Naor Roi Shay , Assaf Ben-Bassat , Limor Zohar , Yishai Eilat
CPC classification number: H03F3/245 , H03F3/45475 , H04B1/04 , H03F2200/451 , H03F2203/45018
Abstract: For example, an apparatus may include an input to receive an input signal in a first voltage domain; a multi-mode power amplifier switchable between a plurality of power modes to generate an output signal based on the input signal; and an output to provide the output signal. For example, the multi-mode power amplifier may be configured to provide the output signal in the first voltage domain at a first power mode, and to provide the output signal in a second voltage domain at a second power mode. For example, a maximal voltage of the second voltage domain may be at least two times a maximal voltage of the first voltage domain.
-
公开(公告)号：US11592339B2
公开(公告)日：2023-02-28
申请号：US16727966
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： Omer Sholev , Elan Banin , Ofir Degani , Assaf Ben-Bassat
Abstract: A device may comprise: a storage for storing a reference output representing an output of an electrical circuit at a reference temperature; one or more processors, configured to: determine a temperature shift based on a comparison of an output of the electrical circuit sensed at a sensing temperature and the reference output; determine a plurality of coefficients of a model of the temperature shift, wherein the model implements one or more functions that associate the plurality of coefficients and a temperature with the temperature shift at the temperature.
-
公开(公告)号：US12149207B2
公开(公告)日：2024-11-19
申请号：US17323189
申请日：2021-05-18
Applicant: Intel Corporation
Inventor： Ofir Degani , Assaf Ben-Bassat , Ashoke Ravi , Ina Shternberg , Naor Shay
Abstract: Techniques are disclosed to allow for a switched capacitor digital power amplifier (PA) that operates using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg.
-
公开(公告)号：US20240113696A1
公开(公告)日：2024-04-04
申请号：US17958340
申请日：2022-10-01
Applicant: INTEL CORPORATION
Inventor： Elan Banin , Rotem Banin , Ashoke Ravi , Assaf Ben-Bassat , Ofir Degani
CPC classification number: H03H11/16 , G06F1/08 , H04L27/2067
Abstract: For example, a phase shifter may include an input to receive an input clock signal having an input frequency and an input phase. For example, the phase shifter may include a quadrature phase-shift generator configured to generate a first signal and a second signal based on the input clock signal, the first and second signals having the input frequency, wherein a phase of the first signal is based on the input phase, wherein a phase of the second signal is shifted by a quadrature phase-shift relative to the phase of the first signal. For example, the phase shifter may include an output to provide an output based on the first signal and the second signal.
-
公开(公告)号：US20230327618A1
公开(公告)日：2023-10-12
申请号：US17705641
申请日：2022-03-28
Applicant: Intel Corporation
Inventor： Ofir Degani , Assaf Ben-Bassat , Yishai Eilat , Naor Roi Shay , Limor Zohar
CPC classification number: H03F3/245 , H03F1/0227 , H03F3/45475
Abstract: Techniques are disclosed to instruct how a switched capacitor digital power amplifier (PA) is configured to operate using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg. The digital PA has a topology that comprises a dual-feedback capacitive path that comprises a capacitive divider and a voltage stabilizing feedback path to selectively couple the capacitive divider to DC bias voltages.
-
Patent Agency Ranking
公开(公告)号：US20220416736A1
公开(公告)日：2022-12-29
申请号：US17359187
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： David Ben-Haim , Ofir Degani , Assaf Ben-Bassat , Anna Nazimov , Naor Shay
Abstract: Various embodiments provide systems, devices, and methods for a multi-core digital power amplifier with an unbalanced power combiner. In one example, two or more cores are combined with a transformer section that has a first coupling coefficient and another two or more cores are combined with a second transformer section that has a second coupling coefficient that is different than the first coupling coefficient. The outputs of different cores may be cross-coupled with the primary inductors of the transformers. The digital power amplifier may provide an output power that is flat over a relatively wide operating range. Other embodiments may be described and claimed.
-
公开(公告)号：US10931384B1
公开(公告)日：2021-02-23
申请号：US16727512
申请日：2019-12-26
Applicant: Intel Corporation
Inventor： Eli Borokhovich , Assaf Ben-Bassat , Shahar Gross , Nahum Kimiagarov
Abstract: A closed loop transmitter (Tx) calibration system is disclosed. The closed loop Tx calibration system comprises a transmitter circuit configured to generate a Tx output signal at a Tx output frequency based on a Tx local oscillator (LO) signal. The closed loop Tx calibration system further comprises a loop back (LPBK) receiver circuit coupled to the transmitter circuit and configured to downconvert the Tx output signal at the Tx output frequency to form an LPBK baseband signal at an LPBK intermediate frequency (IF), based on an LPBK LO signal. In some embodiments, the LPBK IF frequency is different from zero. In some embodiments, the closed loop Tx calibration system further comprises an LO generation circuit configured to generate the Tx LO signal and the LPBK LO signal from a single phase locked loop (PLL) source, based on utilizing a digital to time converter (DTC) circuit.
-
公开(公告)号：US09927775B1
公开(公告)日：2018-03-27
申请号：US15477057
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Rotem Banin , Assaf Ben-Bassat , Evgeny Shumaker , Ofir Degani
CPC classification number: G04F10/005 , H03K19/23
Abstract: A method and apparatus for determining a difference between signal edges in two signals includes a multiple stage converter where each stage determines which of the two signals has an earlier signal edge, outputs a value corresponding to that determination, and then applies a delay to the earlier signal that is equal to half of the delay applied by the next previous stage. The stages examine smaller and smaller intervals to the sought-after signal edge. Each stage includes a plurality of logic elements. If all logic elements in the stage output the same signal, the edge position is clear. If some of the logic elements in the stage vote differently than others in the state due to differences in setup time for the different elements, the edge location has been found within the sensing band of the stage.
-
9.发明公开公开(公告)号：US20230318643A1
公开(公告)日：2023-10-05
申请号：US17710861
申请日：2022-03-31
Applicant: Intel Corporation
Inventor： Elan Banin , Assaf Ben-Bassat , Ashoke Ravi , Rotem Banin , Ofir Degani
CPC classification number: H04B1/10 , H04B1/0028 , H04B1/005 , H04B1/68
Abstract: For example, a transmitter, e.g., for a wireless communication device, may be configured to transmit a wideband Radio Frequency (RF) Transmit (Tx) signal having a wide bandwidth of at least 80 Megahertz (MHz). For example, the transmitter may be configured to generate the wideband RF Tx signal having the wide bandwidth based on a baseband signal. The transmitter may be configured to generate the wideband RF Tx signal including a suppressed third harmonic and a suppressed fifth harmonic.
-
公开(公告)号：US12301317B2
公开(公告)日：2025-05-13
申请号：US17639351
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： Shahar Gross , Assaf Ben-Bassat
Abstract: A device for wireless communications can include a phase selector, a coarse delay line, and a digitally controlled edge interpolator (DCEI). The phase selector receives an input signal and is coupled to the coarse delay line. The coarse delay line can provide one of a plurality of delay ranges. A DCEI, connected to the coarse delay line can provide a fine delay output signal.
-
-
-
-
-
-
-
-
-
Search Results
13
records
(took 0.016 seconds)
