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    PACKET TRANSMISSION SCHEDULING
    3.
    发明申请
    PACKET TRANSMISSION SCHEDULING 有权

    公开(公告)号：US20230061794A1

    公开(公告)日：2023-03-02

    申请号：US17463441

    申请日：2021-08-31

    Applicant: Intel Corporation

    Inventor： Sarig LIVNE ,  Hemanth KRISHNAN ,  Adam CONYERS ,  Chwei King MOK ,  Michael G. LEFEVRE

    IPC: H04J3/16

    Abstract: Examples described herein relate to a network interface device comprising circuitry to cause transmission of packets based on transmission times and use of at least one of multiple time slot granular scheduling lists, wherein the multiple time slot granular scheduling lists comprise at least one list of a first time slot duration and at least one list of a second time slot duration and wherein the first time slot duration is different than the second time slot duration. In some examples, a minimum delay value of a list of the at least one list of a second time slot duration corresponds to a maximum delay value of a list of the at least one list of a first time slot duration. In some examples, the at least one list of a first time slot duration comprises a fine granularity list and the at least one list of a second time slot duration comprises a coarse granularity list.

    2 LAYER ALPHA BASED BUFFER MANAGEMENT WITH DYNAMIC RED
    4.
    发明申请
    2 LAYER ALPHA BASED BUFFER MANAGEMENT WITH DYNAMIC RED 有权

    公开(公告)号：US20230056330A1

    公开(公告)日：2023-02-23

    申请号：US17968713

    申请日：2022-10-18

    Applicant: Intel Corporation

    Inventor： Sarig LIVNE ,  Nrupal JANI ,  Eli SHAPIRO ,  Parthasarathy SARANGAM ,  Neerav PARIKH

    IPC: H04L47/11 ,  H04L49/9005

    Abstract: Methods and apparatus for two-layer Alpha-based buffer management with dynamic RED. A two-layer hierarchical sharing scheme using alpha parameters is provided. A buffer is dynamically shared across upper-level entities, such as hosts, using one set of alpha parameters, then a dynamically-adjusted buffer portion allocated for an upper level entity is shared among its lower level entities (e.g., sub queues) using a separate set of low-level alpha parameters. The memory spaces for the upper- and lower-level entities may be dynamically redistributed. Determinations to drop and/or mark and ECN field of received packets are performed using Dynamic RED, which employs dynamic thresholds and associated dynamic probabilities.

    PACKET TRANSMISSION SCHEDULING FAIRNESS
    5.
    发明申请
    PACKET TRANSMISSION SCHEDULING FAIRNESS 有权

    公开(公告)号：US20220006750A1

    公开(公告)日：2022-01-06

    申请号：US17475197

    申请日：2021-09-14

    Applicant: Intel Corporation

    Inventor： Sarig LIVNE ,  Noam ELATI ,  Hemanth KRISHNAN ,  Venkidesh KRISHNA IYER ,  Adam CONYERS ,  Michael G. LEFEVRE

    IPC: H04L12/851 ,  H04L12/853 ,  H04L12/801 ,  H04L12/26

    Abstract: Examples described herein relate to a network interface device comprising a packet transmission scheduler. In some examples, the packet transmission scheduler is to: perform packet transmit arbitration among nodes, wherein based on a first node of the nodes having transmission paused by flow control, the perform packet transmit arbitration among nodes comprises retain relative priority of a packet departure time for the first node with respect to a second packet departure time associated with a second node of the nodes during a duration of flow control. In some examples, retaining relative priority of a packet departure time for the first node with respect to a second packet departure time associated with a second node of the nodes during a duration of flow control comprises adjust the packet departure time and the second packet departure time to stay within a time window but not rollover.

    LOAD BALANCING AMONG OUTPUT PORTS
    6.
    发明申请
    LOAD BALANCING AMONG OUTPUT PORTS 有权

    公开(公告)号：US20210328929A1

    公开(公告)日：2021-10-21

    申请号：US17359539

    申请日：2021-06-26

    Applicant: Intel Corporation

    Inventor： Boris KLEIMAN ,  Marina POPILOV ,  Anjali Singhai JAIN ,  Piotr UMINSKI ,  Elazar COHEN ,  Kirill KAZATSKER ,  Sarig LIVNE ,  Neerav PARIKH

    IPC: H04L12/803 ,  H04L12/819 ,  H04L12/863 ,  H04L12/923 ,  H04L12/911

    Abstract: Examples described herein relate to a network interface device that includes packet processing circuitry to detect usage of an egress port and report the usage of the egress port to a network interface device driver to cause reallocation of hash-based packet buckets to at least one egress port to provide an allocation of hash-based packet buckets to multiple active egress ports of the network interface device with retention of bucket-to-egress port mappings except for re-allocations of one or more buckets to one or more active egress ports. In some examples, usage of the egress port is based on a count of hash buckets assigned to packets to be transmitted from the egress port or a number of bytes of packets enqueued to be transmitted from the egress port.

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