公开(公告)号：US20240113033A1

公开(公告)日：2024-04-04

申请号：US17956753

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Eng Huat GOH ,  Jiun Hann SIR ,  Poh Boon KHOO ,  Hazwani JAFFAR ,  Hooi San LAM

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a package that includes a die, which may be a processor die, coupled with a first side of a substrate and one or more dies, which may be one or more memory dies, that are coupled with a second side of the substrate opposite the first side of the substrate. All or part of the memory dies may be directly below the die with respect to a plane of the substrate and may be partially or completely within a molding. Other embodiments may be described and/or claimed.

公开(公告)号：US20240355792A1

公开(公告)日：2024-10-24

申请号：US18137360

申请日：2023-04-20

Applicant: Intel Corporation

Inventor： Poh Boon KHOO ,  Jiun Hann SIR ,  Eng Huat GOH ,  Hooi San LAM ,  Hazwani JAFFAR

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H10B80/00 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73204 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Embodiments disclosed herein include electronic packages. In an example, an electronic package includes a package substrate. A die is coupled to the package substrate. The electronic package also includes a memory stack. The memory stack includes a die stack structure coupled to a substrate. The substrate is coupled to and is extending laterally beyond the package substrate. The die stack structure includes a stack of dies and through vias in a mold layer. The die stack structure is laterally spaced apart from the package substrate.