公开(公告)号：US20220230958A1

公开(公告)日：2022-07-21

申请号：US17716937

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Jiun Hann SIR ,  Poh Boon KHOO ,  Eng Huat GOH ,  Amruthavalli Pallavi ALUR ,  Debendra MALLIK

IPC: H01L23/522 ,  H01L23/00

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

公开(公告)号：US20240355792A1

公开(公告)日：2024-10-24

申请号：US18137360

申请日：2023-04-20

Applicant: Intel Corporation

Inventor： Poh Boon KHOO ,  Jiun Hann SIR ,  Eng Huat GOH ,  Hooi San LAM ,  Hazwani JAFFAR

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H10B80/00 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73204 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Embodiments disclosed herein include electronic packages. In an example, an electronic package includes a package substrate. A die is coupled to the package substrate. The electronic package also includes a memory stack. The memory stack includes a die stack structure coupled to a substrate. The substrate is coupled to and is extending laterally beyond the package substrate. The die stack structure includes a stack of dies and through vias in a mold layer. The die stack structure is laterally spaced apart from the package substrate.

公开(公告)号：US20240106139A1

公开(公告)日：2024-03-28

申请号：US17955369

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Jiun Hann SIR ,  Eng Huat GOH ,  Poh Boon KHOO ,  Chin Mian CHOONG ,  Jooi Wah WONG ,  Jia Yun WONG

IPC: H01R12/57 ,  H01L25/065 ,  H01L25/10 ,  H01R12/52 ,  H01R12/79 ,  H01R13/03 ,  H01R13/508 ,  H01R43/20

CPC classification number: H01R12/57 ,  H01L25/0652 ,  H01L25/105 ,  H01R12/526 ,  H01R12/79 ,  H01R13/03 ,  H01R13/508 ,  H01R43/205 ,  H01L24/16

Abstract: Embodiments herein relate to systems, apparatuses, or processes for a connector for a modular memory package that includes one or more memory dies on a substrate, where the connector directly electrically couples electrical contacts at an edge and on each side the substrate of the memory package to electrical contacts at an edge and on each side of another substrate that includes a compute die. The connector may include a first plurality of leads that are substantially parallel with each other, and a second plurality of leads that are substantially parallel with each other that are below the first plurality of leads and electrically couple the two substrates. Other embodiments may be described and/or claimed.

公开(公告)号：US20240071948A1

公开(公告)日：2024-02-29

申请号：US17895112

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Jiun Hann SIR ,  Eng Huat GOH ,  Poh Boon KHOO ,  Nurul Khalidah YUSOP ,  Saw Beng TEOH ,  Chan Kim LEE

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/367 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor package is provided including: a package substrate with a top surface, wherein the top surface extends to a peripheral side surface of the package substrate; a stiffener with a lateral portion and a basket portion, wherein the lateral portion is positioned over the top surface of the package substrate and the basket portion overhangs from the top surface of the package substrate adjacent to the peripheral side surface of the package substrate; at least one semiconductor die positioned in the basket portion of the stiffener; and at least one wire attached to the at least one semiconductor die and extending out of the basket portion of the stiffener.

公开(公告)号：US20230397323A1

公开(公告)日：2023-12-07

申请号：US17834641

申请日：2022-06-07

Applicant: Intel Corporation

Inventor： Min Suet LIM ,  Tin Poay CHUAH ,  Yew San LIM ,  Jeff KU ,  Twan Sing LOO ,  Poh Boon KHOO ,  Jiun Hann SIR

IPC: H05K1/02 ,  H01L23/367 ,  H01L25/065 ,  H01L25/18 ,  H05K3/22 ,  H01L23/42

CPC classification number: H05K1/0204 ,  H01L23/3675 ,  H01L25/0652 ,  H01L25/18 ,  H05K3/22 ,  H01L23/42 ,  H01L2224/32225 ,  H01L24/32

Abstract: Embodiments disclosed herein include a printed circuit board (PCB). In an embodiment, the PCB comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, a first slot is through a thickness of the substrate, and a second slot is through the thickness of the substrate, where the first slot is parallel to the second slot. In an embodiment, a metal plate is provided on the PCB. In an embodiment the metal plate comprises a first portion over the first surface of the substrate between the first slot and the second slot, a second portion connected to the first portion, wherein the second portion is in the first slot, and a third portion connected to the first portion, wherein the third portion is in the second slot.

公开(公告)号：US20240145394A1

公开(公告)日：2024-05-02

申请号：US18050533

申请日：2022-10-28

Applicant: Intel Corporation

Inventor： Poh Boon KHOO ,  Jiun Hann SIR

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/5384 ,  H01L21/4857 ,  H01L23/49816 ,  H01L25/16 ,  H01L28/10

Abstract: The present disclosure is directed to a semiconductor platform having a printed circuit board with an interposer coupled thereto. The interposer includes a low-resistance metal layer that acts as a power corridor, and a first non-conductive layer and a second non-conductive layer, respectively, positioned on the top and bottom surfaces of the metal layer. In addition, the interposer also includes a plurality of vertical interconnects that provide electrical connections through the interposer. A semiconductor package and other components may be coupled to the interposer, for which the interposer provides a power corridor for the semiconductor package and the components, and to the print circuit board via the plurality of vertical interconnects.

公开(公告)号：US20240136278A1

公开(公告)日：2024-04-25

申请号：US18400784

申请日：2023-12-29

Applicant: Intel Corporation

Inventor： Jiun Hann SIR ,  Poh Boon KHOO ,  Eng Huat GOH ,  Amruthavalli Pallavi ALUR ,  Debendra MALLIK

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L24/09 ,  H01L24/17 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2924/01029

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

公开(公告)号：US20240006338A1

公开(公告)日：2024-01-04

申请号：US17857053

申请日：2022-07-04

Applicant: Intel Corporation

Inventor： Poh Boon KHOO ,  Jiun Hann SIR ,  Min Suet LIM ,  Seok Ling LIM ,  Yew San LIM

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L23/49816

Abstract: A semiconductor package including a package substrate including a bottom surface; a first plurality of solder balls connected to the bottom surface of the package substrate; a second plurality of solder balls connected to a motherboard; and a shielding assembly interposed between the first and the second plurality of solder balls and configured to shield each solder ball of the first and second plurality of solder balls from electromagnetic interference.

公开(公告)号：US20250096154A1

公开(公告)日：2025-03-20

申请号：US18466844

申请日：2023-09-14

Applicant: Intel Corporation

Inventor： Chin Mian CHOONG ,  Jiun Hann SIR ,  Poh Boon KHOO ,  Juha PAAVOLA

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498 ,  H01L23/552

Abstract: The present disclosure is directed to a stiffener having a first lateral member and a vertical member that form a frame structure that encloses around a package substrate of a semiconductor package, and the vertical member having an upper end connected to the first lateral member and a lower end extending downward from the first lateral member for connecting to a printed circuit board.

公开(公告)号：US20240113033A1

公开(公告)日：2024-04-04

申请号：US17956753

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Eng Huat GOH ,  Jiun Hann SIR ,  Poh Boon KHOO ,  Hazwani JAFFAR ,  Hooi San LAM

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a package that includes a die, which may be a processor die, coupled with a first side of a substrate and one or more dies, which may be one or more memory dies, that are coupled with a second side of the substrate opposite the first side of the substrate. All or part of the memory dies may be directly below the die with respect to a plane of the substrate and may be partially or completely within a molding. Other embodiments may be described and/or claimed.