公开(公告)号：US20230200063A1

公开(公告)日：2023-06-22

申请号：US17559725

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Chang Wan Ha ,  Md Rezaul Karim Nishat ,  Liu Liu ,  Yuanrong Shui ,  Kwame Eason ,  Ahmed Reza ,  Hoon Koh

IPC: H01L27/11578 ,  H01L27/11551 ,  H01L23/48 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/04 ,  G11C8/14

CPC classification number: H01L27/11578 ,  H01L27/11551 ,  H01L23/481 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/0483 ,  G11C8/14

Abstract: Systems, apparatuses, and methods may provide for technology that arranges stair wells for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a first through array via area and a first staircase area coupled to a plurality of decks. The first staircase area includes a first stair well and a second stair well located contiguous to the first stair well.

公开(公告)号：US20220399057A1

公开(公告)日：2022-12-15

申请号：US17343584

申请日：2021-06-09

Applicant: Intel Corporation

Inventor： Chang Wan Ha ,  Deepak Thimmegowda ,  Hoon Koh ,  Richard M. Gularte ,  Liu Liu ,  David Meyaard ,  Ahsanur Rahman

IPC: G11C16/04

Abstract: An embodiment of a memory device may include a full block memory array of a lower tile of 3D NAND string memory cells, a full block memory array of an upper tile of 3D NAND string memory cells, a first portion of a string driver circuit coupled to the full block memory array of the lower tile, a second portion of the string driver circuit coupled to the full block memory array of the upper tile, a first split block memory array of the lower tile coupled to the first portion of the string driver circuit, and a second split block memory array of the upper tile coupled to the second portion of the string driver circuit. Other embodiments are disclosed and claimed.