公开(公告)号：US20230076831A1

公开(公告)日：2023-03-09

申请号：US17469634

申请日：2021-09-08

Applicant: Intel Corporation

Inventor： Praveen Kumar Kalsani ,  Ahmed Reza ,  Liu Liu ,  Deepak Thimmegowda ,  Zengtao Tony Liu ,  Sriram Balasubrahmanyam

IPC: H01L27/11575 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582

Abstract: An embodiment of a memory device may include a substrate, a first memory array of three-dimensional (3D) NAND cells disposed on the substrate, an isolation trench disposed on the substrate adjacent to the first memory array, and an input/output (IO) contact positioned within the isolation trench. Other embodiments are disclosed and claimed.

公开(公告)号：US20230200063A1

公开(公告)日：2023-06-22

申请号：US17559725

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Chang Wan Ha ,  Md Rezaul Karim Nishat ,  Liu Liu ,  Yuanrong Shui ,  Kwame Eason ,  Ahmed Reza ,  Hoon Koh

IPC: H01L27/11578 ,  H01L27/11551 ,  H01L23/48 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/04 ,  G11C8/14

CPC classification number: H01L27/11578 ,  H01L27/11551 ,  H01L23/481 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/0483 ,  G11C8/14

Abstract: Systems, apparatuses, and methods may provide for technology that arranges stair wells for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a first through array via area and a first staircase area coupled to a plurality of decks. The first staircase area includes a first stair well and a second stair well located contiguous to the first stair well.

公开(公告)号：US20220399057A1

公开(公告)日：2022-12-15

申请号：US17343584

申请日：2021-06-09

Applicant: Intel Corporation

Inventor： Chang Wan Ha ,  Deepak Thimmegowda ,  Hoon Koh ,  Richard M. Gularte ,  Liu Liu ,  David Meyaard ,  Ahsanur Rahman

IPC: G11C16/04

Abstract: An embodiment of a memory device may include a full block memory array of a lower tile of 3D NAND string memory cells, a full block memory array of an upper tile of 3D NAND string memory cells, a first portion of a string driver circuit coupled to the full block memory array of the lower tile, a second portion of the string driver circuit coupled to the full block memory array of the upper tile, a first split block memory array of the lower tile coupled to the first portion of the string driver circuit, and a second split block memory array of the upper tile coupled to the second portion of the string driver circuit. Other embodiments are disclosed and claimed.

公开(公告)号：US12167592B2

公开(公告)日：2024-12-10

申请号：US17442582

申请日：2019-06-10

Applicant: INTEL CORPORATION

Inventor： Nanda Kumar Chakravarthi ,  David Meyaard ,  Abhinav Tripathi ,  Liu Liu

IPC: H01L27/11524 ,  H10B41/20 ,  H10B41/35 ,  H10B43/20 ,  H10B43/35

Abstract: Embodiments of the present disclosure are directed towards a memory device including a top wordline contact located in a region that is protected from erosion during a planarization process, e.g., chemical mechanical polish (CMP). In embodiments, a plurality of wordlines are formed in a stack of multiple layers and a plurality of wordline contacts are formed to intersect with the plurality of wordlines. In embodiments, the stack forms a staircase and each of the plurality of wordline contacts lands on a corresponding each of the wordlines proximate to an edge of the staircase such that a top wordline contact lands in a region on a top wordline previously covered by a sacrificial layer. In some embodiments, the region is proximate to a raised notch at an edge of the staircase. Other embodiments may be described and claimed.