公开(公告)号：US20230200063A1

公开(公告)日：2023-06-22

申请号：US17559725

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Chang Wan Ha ,  Md Rezaul Karim Nishat ,  Liu Liu ,  Yuanrong Shui ,  Kwame Eason ,  Ahmed Reza ,  Hoon Koh

IPC: H01L27/11578 ,  H01L27/11551 ,  H01L23/48 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/04 ,  G11C8/14

CPC classification number: H01L27/11578 ,  H01L27/11551 ,  H01L23/481 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/0483 ,  G11C8/14

Abstract: Systems, apparatuses, and methods may provide for technology that arranges stair wells for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a first through array via area and a first staircase area coupled to a plurality of decks. The first staircase area includes a first stair well and a second stair well located contiguous to the first stair well.

公开(公告)号：US20230076831A1

公开(公告)日：2023-03-09

申请号：US17469634

申请日：2021-09-08

Applicant: Intel Corporation

Inventor： Praveen Kumar Kalsani ,  Ahmed Reza ,  Liu Liu ,  Deepak Thimmegowda ,  Zengtao Tony Liu ,  Sriram Balasubrahmanyam

IPC: H01L27/11575 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582

Abstract: An embodiment of a memory device may include a substrate, a first memory array of three-dimensional (3D) NAND cells disposed on the substrate, an isolation trench disposed on the substrate adjacent to the first memory array, and an input/output (IO) contact positioned within the isolation trench. Other embodiments are disclosed and claimed.