公开(公告)号：US20200218677A1

公开(公告)日：2020-07-09

申请号：US16819283

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Jacob Jun Pan ,  Ashok Raj ,  Srinivas Pandruvada

IPC: G06F13/24

Abstract: In an embodiment, a processor for performance state adjustment includes a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU). The IOMMU is to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit. The notification indicates the destination PE for the user interrupt. The power control unit is to adjust a performance state of the destination PE in response to the notification of the user interrupt. Other embodiments are described and claimed.

公开(公告)号：US10599596B2

公开(公告)日：2020-03-24

申请号：US15864290

申请日：2018-01-08

Applicant: Intel Corporation

Inventor： Jacob Jun Pan ,  Ashok Raj ,  Srinivas Pandruvada

IPC: G06F13/10 ,  G06F13/24 ,  G06F15/80 ,  G06F9/30

Abstract: In an embodiment, a processor for performance state adjustment includes a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU). The IOMMU is to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit. The notification indicates the destination PE for the user interrupt. The power control unit is to adjust a performance state of the destination PE in response to the notification of the user interrupt. Other embodiments are described and claimed.

公开(公告)号：US20240338238A1

公开(公告)日：2024-10-10

申请号：US18574849

申请日：2022-01-26

Applicant: Intel Corporation

Inventor： Wei Wang ,  Kun Tian ,  Guang Zeng ,  Gilbert Neiger ,  Rajesh Sankaran ,  Asit Mallick ,  Jr-Shian Tsai ,  Jacob Jun Pan ,  Mesut Ergin

IPC: G06F9/455 ,  G06F9/30

CPC classification number: G06F9/45558 ,  G06F9/3016 ,  G06F9/45545 ,  G06F2009/45579

Abstract: A method and system of host to guest (H2G) notification are disclosed. H2G is provided via an instruction. The instruction is a send user inter-processor interrupt instruction. An exemplary processor includes decoder circuitry to decode a single instruction and execute the decoded single instruction according to the at least the opcode to cause a host to guest notification from a virtual device running in a host machine on the first physical processor to a virtual device driver running on a virtual processor in a guest machine on a second physical processor.

公开(公告)号：US20190102274A1

公开(公告)日：2019-04-04

申请号：US15720585

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Hisham Abu Salah ,  Arthur Leonard Brown ,  Russell J. Fenger ,  Deepak Samuel Kirubakaran ,  Asit K. Mallick ,  Jacob Jun Pan ,  Srinivas Pandruvada ,  Efraim Rotem ,  Arjan Van De Ven ,  Eliezer Weissmann ,  Rafal J. Wysocki

IPC: G06F11/34 ,  G06F9/48 ,  G06F9/50

Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.

公开(公告)号：US20200278914A1

公开(公告)日：2020-09-03

申请号：US16647563

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： HISHAM ABU SALAH ,  Arthur Leonard Brown ,  Russell J. Fenger ,  Deepak Samuel Kirubakaran ,  Asit K. Mallick ,  Jacob Jun Pan ,  Srinivas Pandruvada ,  Efraim Rotem ,  Arjan Van De Ven ,  Eliezer Weissmann ,  Rafal J. Wysocki

IPC: G06F11/34 ,  G06F11/30 ,  G06F9/48 ,  G06F9/50

Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.

公开(公告)号：US20190213153A1

公开(公告)日：2019-07-11

申请号：US15864290

申请日：2018-01-08

Applicant: Intel Corporation

Inventor： Jacob Jun Pan ,  Ashok Raj ,  Srinivas Pandruvada

IPC: G06F13/24

Abstract: In an embodiment, a processor for performance state adjustment includes a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU). The IOMMU is to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit. The notification indicates the destination PE for the user interrupt. The power control unit is to adjust a performance state of the destination PE in response to the notification of the user interrupt. Other embodiments are described and claimed.