公开(公告)号：US11442760B2

公开(公告)日：2022-09-13

申请号：US15200725

申请日：2016-07-01

申请人： Intel Corporation

发明人： Barry E. Huntley ,  Jr-Shian Tsai ,  Gilbert Neiger ,  Rajesh M. Sankaran ,  Mesut A. Ergin ,  Ravi L. Sahita ,  Andrew J. Herdrich ,  Wei Wang

IPC分类号： G06F9/455 ,  G06F9/30 ,  G06F12/02 ,  G06F12/109 ,  G06F12/10 ,  G11C7/10

摘要： A processor of an aspect includes a decode unit to decode an aperture access instruction, and an execution unit coupled with the decode unit. The execution unit, in response to the aperture access instruction, is to read a host physical memory address, which is to be associated with an aperture that is to be in system memory, from an access protected structure, and access data within the aperture at a host physical memory address that is not to be obtained through address translation. Other processors are also disclosed, as are methods, systems, and machine-readable medium storing aperture access instructions.

公开(公告)号：US20190205737A1

公开(公告)日：2019-07-04

申请号：US15859504

申请日：2017-12-30

申请人： Intel Corporation

发明人： Amit Bleiweiss ,  Anavai Ramesh ,  Asit Mishra ,  Deborah Marr ,  Jeffrey Cook ,  Srinivas Sridharan ,  Eriko Nurvitadhi ,  Elmoustapha Ould-Ahmed-Vall ,  Dheevatsa Mudigere ,  Mohammad Ashraf Bhuiyan ,  Md Faijul Amin ,  Wei Wang ,  Dhawal Srivastava ,  Niharika Maheshwari

IPC分类号： G06N3/063 ,  G06N3/08 ,  G06F7/78 ,  G06T1/20

CPC分类号： G06N3/063 ,  G06F7/78 ,  G06N3/084 ,  G06T1/20

摘要： An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

公开(公告)号：US09934176B2

公开(公告)日：2018-04-03

申请号：US14582785

申请日：2014-12-24

申请人： Intel Corporation

发明人： Wei Wang ,  Hsiao-Ping J. Tsai ,  Jongbae Park

IPC分类号： G06F13/28 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F13/287 ,  G06F13/4022 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

摘要： An apparatus for transceiver multiplexing over USB Type-C interconnects is described herein. The apparatus includes a processor, a memory, a USB Type-C connector, a first transmitter, a multiplexed transmitter, a multiplexed receiver, and an on-die inductor. The multiplexed transmitter, when disabled, enables the multiplexed receiver to be in communication over a channel with a second transmitter over the USB Type C connector. The multiplexed receiver, when disabled, enables the multiplexed transmitter to be in communication over the channel with a receiver over the USB Type-C connector. The on-die inductor is disposed in serial with the multiplexed transmitter, and disposed in parallel with the multiplexed receiver. The on-die inductor reduces: effective shunt capacitance and insertion loss between the multiplexed transmitter and the channel; effective shunt capacitance and insertion loss between the channel and the multiplexed receiver.

公开(公告)号：US20230053289A1

公开(公告)日：2023-02-16

申请号：US17845794

申请日：2022-06-21

申请人： Intel Corporation

发明人： Amit Bleiweiss ,  Anavai Ramesh ,  Asit Mishra ,  Deborah Marr ,  Jeffrey Cook ,  Srinivas Sridharan ,  Eriko Nurvitadhi ,  Elmoustapha Ould-Ahmed-Vall ,  Dheevatsa Mudigere ,  Mohammad Ashraf Bhuiyan ,  Md Faijul Amin ,  Wei Wang ,  Dhawal Srivastava ,  Niharika Maheshwari

IPC分类号： G06N3/063 ,  G06F7/78 ,  G06N3/08 ,  G06N20/00 ,  G06F9/00

摘要： An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

公开(公告)号：US11412059B2

公开(公告)日：2022-08-09

申请号：US16328865

申请日：2016-09-30

申请人： INTEL CORPORATION

发明人： Huawei Xie ,  Jun Nakajima ,  David E. Cohen ,  Mesut A. Ergin ,  Wei Wang

IPC分类号： H04L67/568 ,  H04L49/90 ,  G06F9/455

摘要： Technologies for managing paravirtual network device queue and memory of a network computing device that includes multi-core processor, a multi-layer cache, a host, and a plurality of virtual machine instances. The host is assigned a processor core of the processor and may be configured to copy a received network packet to a last level cache of the multi-layer cache and determine one or more virtual machine instances configured to process the received network packet. Each virtual machine instance has been assigned a processor core of the processor and has been allocated a first level cache of the multi-level cache memory associated with the respective processor core. The host is additionally configured to inject an interrupt into each processor core of the determined virtual machine (s) which indicates to the virtual machine instance (s) that the received network packet is available to be processed.

公开(公告)号：US20180004562A1

公开(公告)日：2018-01-04

申请号：US15200725

申请日：2016-07-01

申请人： Intel Corporation

发明人： Barry E. Huntley ,  Jr-Shian Tsai ,  Gilbert Neiger ,  Rajesh M. Sankaran ,  Mesut A. Ergin ,  Ravi L. Sahita ,  Andrew J. Herdrich ,  Wei Wang

IPC分类号： G06F9/455 ,  G06F12/10 ,  G11C7/10

CPC分类号： G06F9/45558 ,  G06F9/3004 ,  G06F9/45533 ,  G06F12/0292 ,  G06F12/10 ,  G06F12/109 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2009/45595 ,  G06F2212/151 ,  G11C7/1072

摘要： A processor of an aspect includes a decode unit to decode an aperture access instruction, and an execution unit coupled with the decode unit. The execution unit, in response to the aperture access instruction, is to read a host physical memory address, which is to be associated with an aperture that is to be in system memory, from an access protected structure, and access data within the aperture at a host physical memory address that is not to be obtained through address translation. Other processors are also disclosed, as are methods, systems, and machine-readable medium storing aperture access instructions.

公开(公告)号：US09922248B2

公开(公告)日：2018-03-20

申请号：US14865401

申请日：2015-09-25

申请人： Intel Corporation

发明人： Mingming Xu ,  Stefano Giaconi ,  Wei Wang

IPC分类号： H04L27/14 ,  G06K9/00 ,  G01R13/02

CPC分类号： G06K9/0053 ,  G01R13/02 ,  G06K9/00503 ,  G06K9/00557 ,  G06K9/00604

摘要： Some embodiments include apparatuses and methods having a receiver unit included in a die and a measurement unit included in the die. The receiver unit includes a sampler to sample a first signal based on timing of a first clock signal to generate a second signal. The measurement unit is arranged to sample the first signal based on timing of a second clock signal to provide information for generation of a graph presenting an eye scan of the first signal. The second clock signal has a frequency asynchronous with a frequency of the first clock signal.

公开(公告)号：US20160188506A1

公开(公告)日：2016-06-30

申请号：US14582785

申请日：2014-12-24

申请人： Intel Corporation

发明人： Wei Wang ,  Hsiao-Ping J. Tsai ,  Jongbae Park

IPC分类号： G06F13/28 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F13/287 ,  G06F13/4022 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

摘要： An apparatus for transceiver multiplexing over USB Type-C interconnects is described herein. The apparatus includes a processor, a memory, a USB Type-C connector, a first transmitter, a multiplexed transmitter, a multiplexed receiver, and an on-die inductor. The multiplexed transmitter, when disabled, enables the multiplexed receiver to be in communication over a channel with a second transmitter over the USB Type C connector. The multiplexed receiver, when disabled, enables the multiplexed transmitter to be in communication over the channel with a receiver over the USB Type-C connector. The on-die inductor is disposed in serial with the multiplexed transmitter, and disposed in parallel with the multiplexed receiver. The on-die inductor reduces: effective shunt capacitance and insertion loss between the multiplexed transmitter and the channel; effective shunt capacitance and insertion loss between the channel and the multiplexed receiver.

摘要翻译： 本文描述了用于通过USB C型互连的收发器复用的装置。 该装置包括处理器，存储器，USB Type-C连接器，第一发射器，多路复用发射器，多路复用接收器和片上电感器。 多路复用的发射机在被禁用时，使多路复用的接收机能够通过USB C型连接器上的第二个发射机在一个信道上进行通信。 多路复用的接收器在禁用时，使多路复用的发射机能够通过USB Type-C连接器上的接收器在信道上进行通信。 片上电感器与复用的发射机串联设置，并且与多路复用的接收机并行布置。 片上电感降低了多路复用发射机和信道之间的有效分流电容和插入损耗; 有效的分流电容和通道与复用的接收器之间的插入损耗。

公开(公告)号：US11373088B2

公开(公告)日：2022-06-28

申请号：US15859504

申请日：2017-12-30

申请人： Intel Corporation

发明人： Amit Bleiweiss ,  Anavai Ramesh ,  Asit Mishra ,  Deborah Marr ,  Jeffrey Cook ,  Srinivas Sridharan ,  Eriko Nurvitadhi ,  Elmoustapha Ould-Ahmed-Vall ,  Dheevatsa Mudigere ,  Mohammad Ashraf Bhuiyan ,  Md Faijul Amin ,  Wei Wang ,  Dhawal Srivastava ,  Niharika Maheshwari

IPC分类号： G06N3/063 ,  G06N20/00 ,  G06F7/78 ,  G06N3/08 ,  G06F9/00 ,  G06T1/20

摘要： An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.