公开(公告)号：US09665527B2

公开(公告)日：2017-05-30

申请号：US14565176

申请日：2014-12-09

申请人： Intel Corporation

发明人： Christopher P Mozak ,  James A McCall ,  Bryan K Casper

IPC分类号： G06F13/20 ,  G06F13/42 ,  G06F13/40

CPC分类号： G06F13/1657 ,  G06F11/10 ,  G06F13/4004 ,  G06F13/4022 ,  G06F13/4072 ,  G06F13/4217 ,  G06F13/4221 ,  G06F13/4234 ,  H04L25/4915 ,  Y02D10/14 ,  Y02D10/151

摘要： Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

公开(公告)号：US10025685B2

公开(公告)日：2018-07-17

申请号：US14670411

申请日：2015-03-27

申请人： Intel Corporation

发明人： James A McCall ,  Kuljit S Bains

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F11/30 ,  G06F13/42 ,  G11C7/10 ,  G11C29/02 ,  G11C29/50

摘要： A memory subsystem manages memory I/O impedance compensation by the memory device monitoring a need for impedance compensation. Instead of a memory controller regularly sending a signal to have the memory device update the impedance compensation when a change is not needed, the memory device can indicate when it is ready to perform an impedance compensation change. The memory controller can send an impedance compensation signal to the memory device in response to a compensation flag set by the memory or in response to determining that a sensor value has changed in excess of a threshold.

公开(公告)号：US09595963B2

公开(公告)日：2017-03-14

申请号：US14838373

申请日：2015-08-28

申请人： Intel Corporation

发明人： James A McCall ,  Kuljit S Bains

IPC分类号： H03K17/16 ,  H03K19/00 ,  G11C7/10

CPC分类号： H03K19/0005 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/4074 ,  G11C11/4093

摘要： Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.

摘要翻译： 这里描述了一种用于响应于终止信号电平在存储器的存储器输入 - 输出（I / O）接口之间动态切换一个或多个有限终端阻抗值设置的方法和装置。 该方法包括：为存储器的输入输出（I / O）接口的终端单元设置第一终端阻抗值设置; 当所述存储器未被访问时，将所述第一终端阻抗值设置分配给所述终端单元; 以及响应于终止信号电平从第一终端阻抗值设置切换到第二终端阻抗值设置。