公开(公告)号：US11189487B2

公开(公告)日：2021-11-30

申请号：US16330366

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Jonathan E. Leonard ,  Aravind S. Killampalli ,  Chad Byers ,  Jay P. Gupta

IPC: H01L21/02 ,  H01L21/67

Abstract: A high-pressure dielectric film curing apparatus, such as a high-pressure batch furnace, is controlled to an elevated cure temperature and super-atmospheric pressure for the duration of the film curing time with the cure pressure achieved at least partially with a vapor of aqueous ammonia in fluid communication with the chamber. The cure temperature may vary, for example between 175° C., and 400° C., or more. The cure pressure may also vary as limited by the saturated water vapor pressure, for example between 100 PSIA and 300 PSIA, or more. The aqueous ammonia may be injected into the chamber or vaporized upstream of the chamber. One or more carrier and/or diluent gas (vapor) may be introduced into the chamber to adjust the partial pressure of ammonia vapor, water vapor, and the diluent.

公开(公告)号：US11532619B2

公开(公告)日：2022-12-20

申请号：US16367175

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Jack Kavalieros ,  Caleb Barrett ,  Jay P. Gupta ,  Nishant Gupta ,  Kaiwen Hsu ,  Byungki Jung ,  Aravind S. Killampalli ,  Justin Railsback ,  Supanee Sukrittanon ,  Prashant Wadhwa

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/423

Abstract: Transistor structures including a non-planar body that has an active portion comprising a semiconductor material of a first height that is variable, and an inactive portion comprising an oxide of the semiconductor material of a second variable height, complementary to the first height. Gate electrodes and source/drain terminals may be coupled through a transistor channel having any width that varies according to the first height. Oxidation of a semiconductor material may be selectively catalyzed to convert a desired portion of a non-planar body into the oxide of the semiconductor material. Oxidation may be enhanced through the application of a catalyst, such as one comprising metal and oxygen, for example.

公开(公告)号：US10811251B2

公开(公告)日：2020-10-20

申请号：US16324859

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Jeanne L. Luce ,  Ebony L. Mays ,  Aravind S. Killampalli ,  Jay P. Gupta

IPC: H01L21/02 ,  C23C16/56 ,  H01L21/205 ,  H01L21/768 ,  H01L23/538 ,  H01L23/498 ,  H01L23/14

Abstract: A flowable chemical vapor deposition method including depositing a dielectric film precursor on a substrate in a flowable form; depositing an oligomerization agent on the substrate; forming a dielectric film from the dielectric film precursor; and curing the dielectric film under a pressure greater than atmospheric pressure. A method including depositing a dielectric film precursor as a liquid on a substrate in the presence of an oligomerization agent; treating the deposited dielectric film precursor to inhibit outgassing; and curing the dielectric film precursor to form a dielectric film. A method including delivering a dielectric film precursor as a vapor to a substrate including gap structures between device features; condensing the dielectric film precursor on the substrate to a liquid; flowing the liquid into the gap structures; and curing the dielectric film precursor under a pressure of 15 pounds per square inch gauge or greater.

公开(公告)号：US10573809B2

公开(公告)日：2020-02-25

申请号：US16077571

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Ravi Pillarisetty ,  Uday Shah ,  Elijah V. Karpov ,  Niloy Mukherjee ,  Pulkit Jain ,  Aravind S. Killampalli ,  Jay P. Gupta ,  James S. Clarke

IPC: H01L45/00

Abstract: An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; and an oxide layer between the OEL and the bottom electrode; wherein the oxide layer includes Deuterium and oxygen vacancies. Other embodiments are described herein.

公开(公告)号：US20190036020A1

公开(公告)日：2019-01-31

申请号：US16077571

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Ravi Pillarisetty ,  Uday Shah ,  Elijah V. Karpov ,  Niloy Mukherjee ,  Pulkit Jain ,  Aravind S. Killampalli ,  Jay P. Gupta ,  James S. Clarke

IPC: H01L45/00

CPC classification number: H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1641

Abstract: An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; and an oxide layer between the OEL and the bottom electrode; wherein the oxide layer includes Deuterium and oxygen vacancies. Other embodiments are described herein.