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    Method and apparatus for high pressure cure of flowable dielectric films
    4.
    发明授权
    Method and apparatus for high pressure cure of flowable dielectric films 有权

    公开(公告)号：US11189487B2

    公开(公告)日：2021-11-30

    申请号：US16330366

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Jonathan E. Leonard ,  Aravind S. Killampalli ,  Chad Byers ,  Jay P. Gupta

    IPC: H01L21/02 ,  H01L21/67

    Abstract: A high-pressure dielectric film curing apparatus, such as a high-pressure batch furnace, is controlled to an elevated cure temperature and super-atmospheric pressure for the duration of the film curing time with the cure pressure achieved at least partially with a vapor of aqueous ammonia in fluid communication with the chamber. The cure temperature may vary, for example between 175° C., and 400° C., or more. The cure pressure may also vary as limited by the saturated water vapor pressure, for example between 100 PSIA and 300 PSIA, or more. The aqueous ammonia may be injected into the chamber or vaporized upstream of the chamber. One or more carrier and/or diluent gas (vapor) may be introduced into the chamber to adjust the partial pressure of ammonia vapor, water vapor, and the diluent.

    Deuterium-based passivation of non-planar transistor interfaces
    5.
    发明授权
    Deuterium-based passivation of non-planar transistor interfaces 有权

    公开(公告)号：US11094785B2

    公开(公告)日：2021-08-17

    申请号：US16876528

    申请日：2020-05-18

    Applicant: INTEL CORPORATION

    Inventor： Prashant Majhi ,  Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani ,  Aravind S. Killampalli ,  Mark R. Brazier ,  Jaya P. Gupta

    IPC: H01L29/10 ,  H01L29/775 ,  H01L21/30 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

    Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides. Such interfaces are common locations of trap sites that may include impurities, incomplete bonds dangling bonds, and broken bonds, for example, and thus such interfaces can benefit from deuterium-based passivation to improve the performance and reliability of the transistor.

    WRAP-AROUND CONTACT WITH REDUCED RESISTANCE
    6.
    发明公开
    WRAP-AROUND CONTACT WITH REDUCED RESISTANCE 审中-公开

    公开(公告)号：US20230187507A1

    公开(公告)日：2023-06-15

    申请号：US17547980

    申请日：2021-12-10

    Applicant: Intel Corporation

    Inventor： Prashant Majhi ,  Anand Murthy ,  Aravind S. Killampalli

    IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

    CPC classification number: H01L29/41733 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

    Abstract: An integrated circuit includes a body of semiconductor material. A source or drain region includes semiconductor material in contact with the body, where the semiconductor material of the source or drain region includes an outer region having a dopant concentration that is greater than a remaining region of the source or drain region, the outer region defining multiple contact surfaces of the source or drain region and extending into the source or drain region to a depth of at least 1 nm. A contact comprising a metal is on the multiple contact surfaces of the source or drain region. The dopant concentration of the outer region is continuous along the entire interface between the contact and the outer region, according to an example.

    Dielectric gap-fill material deposition
    7.
    发明授权
    Dielectric gap-fill material deposition 有权

    公开(公告)号：US10811251B2

    公开(公告)日：2020-10-20

    申请号：US16324859

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Jeanne L. Luce ,  Ebony L. Mays ,  Aravind S. Killampalli ,  Jay P. Gupta

    IPC: H01L21/02 ,  C23C16/56 ,  H01L21/205 ,  H01L21/768 ,  H01L23/538 ,  H01L23/498 ,  H01L23/14

    Abstract: A flowable chemical vapor deposition method including depositing a dielectric film precursor on a substrate in a flowable form; depositing an oligomerization agent on the substrate; forming a dielectric film from the dielectric film precursor; and curing the dielectric film under a pressure greater than atmospheric pressure. A method including depositing a dielectric film precursor as a liquid on a substrate in the presence of an oligomerization agent; treating the deposited dielectric film precursor to inhibit outgassing; and curing the dielectric film precursor to form a dielectric film. A method including delivering a dielectric film precursor as a vapor to a substrate including gap structures between device features; condensing the dielectric film precursor on the substrate to a liquid; flowing the liquid into the gap structures; and curing the dielectric film precursor under a pressure of 15 pounds per square inch gauge or greater.

    Deuterium-based passivation of non-planar transistor interfaces
    8.
    发明授权
    Deuterium-based passivation of non-planar transistor interfaces 有权

    公开(公告)号：US10692974B2

    公开(公告)日：2020-06-23

    申请号：US15753739

    申请日：2015-09-18

    Applicant: INTEL CORPORATION

    Inventor： Prashant Majhi ,  Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani ,  Aravind S. Killampalli ,  Mark R. Brazier ,  Jaya P. Gupta

    IPC: H01L29/10 ,  H01L29/775 ,  H01L21/30 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

    Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides. Such interfaces are common locations of trap sites that may include impurities, incomplete bonds dangling bonds, and broken bonds, for example, and thus such interfaces can benefit from deuterium-based passivation to improve the performance and reliability of the transistor.

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