公开(公告)号：US20240303343A1

公开(公告)日：2024-09-12

申请号：US18666693

申请日：2024-05-16

Applicant: Intel Corporation

Inventor： Yi ZENG ,  Russell J. WUNDERLICH ,  Janusz JURSKI ,  Lumin ZHANG ,  Kasper WSZOLEK ,  Jeanne GUILLORY ,  Ching Yu LO ,  Teresa C. HERRICK ,  Richard Marian THOMAIYAR

IPC: G06F21/57 ,  G06F1/06

CPC classification number: G06F21/575 ,  G06F1/06 ,  G06F21/572

Abstract: Examples described herein relate to multiple processor sockets comprising processors connected thereto and first circuitry. The first circuitry is to: based on a first mode of operation: configure the multiple processor sockets to operate with a single memory address space and share interfaces and based on a second mode of operation: configure the interfaces accessible to the multiple processor sockets to provide isolated communications to processor sockets in different partitions and configure the multiple processor sockets to operate in independent memory address spaces.

公开(公告)号：US20190108347A1

公开(公告)日：2019-04-11

申请号：US16213962

申请日：2018-12-07

Applicant: Intel Corporation

Inventor： Sergiu D. GHETIE ,  Wojciech POWIERTOWSKI ,  Jeanne GUILLORY ,  Neeraj S. UPASANI ,  Srihari NARAYANAN ,  Mohan J. KUMAR ,  Sagar V. DALVI

IPC: G06F21/57 ,  G06F9/4401 ,  G06F9/22

Abstract: A processor can be configured to access boot firmware from a remote location independent from use of a chipset. After a processor powers-on or reboots, the processor can execute microcode. The microcode will cause the processor to train a link with a remote device. The remote device can provide the processor with access to boot firmware. The processor can copy the boot firmware to the processor's cache or memory. The processor will attempt to authenticate the boot firmware. If the boot firmware is authenticated, the processor executes the copy of the boot firmware.