公开(公告)号：US20150108660A1

公开(公告)日：2015-04-23

申请号：US14588183

申请日：2014-12-31

Applicant: Intel Corporation

Inventor： Pete Vogt ,  Andre Schaefer ,  Warren Morrow ,  John Halbert ,  Jin Kim ,  Kenneth Shoemaker

IPC: H01L25/065 ,  G11C5/06 ,  H01L27/108 ,  H01L23/48

CPC classification number: H01L25/0657 ,  G11C5/06 ,  H01L23/481 ,  H01L24/16 ,  H01L27/108 ,  H01L27/10882 ,  H01L27/10897 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541

Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

Abstract translation: 具有提供偏移互连的接口的堆叠存储器。 存储器件的实施例包括与系统元件耦合的系统元件和存储器堆栈，存储器堆栈包括一个或多个存储器管芯层。 每个存储器管芯层包括第一面和第二面，每个存储管芯层的第二面包括用于将存储管芯层的数据接口引脚与耦合元件的第一面的数据接口引脚耦合的接口。 每个存储器管芯层的接口包括在存储管芯层的每个数据接口引脚和耦合元件的数据接口引脚的相应数据接口引脚之间提供偏移的连接。

公开(公告)号：US09768148B2

公开(公告)日：2017-09-19

申请号：US14588183

申请日：2014-12-31

Applicant: Intel Corporation

Inventor： Pete Vogt ,  Andre Schaefer ,  Warren Morrow ,  John Halbert ,  Jin Kim ,  Kenneth Shoemaker

IPC: G11C5/06 ,  H01L25/065 ,  H01L27/108 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  G11C5/06 ,  H01L23/481 ,  H01L24/16 ,  H01L27/108 ,  H01L27/10882 ,  H01L27/10897 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541

Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

公开(公告)号：US09824743B2

公开(公告)日：2017-11-21

申请号：US15585678

申请日：2017-05-03

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Kuljit Bains ,  John Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4094

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096

Abstract: Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.