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公开(公告)号:US11437693B2
公开(公告)日:2022-09-06
申请号:US16764600
申请日:2017-12-30
Applicant: Intel Corporation
Inventor: Georgios C. Dogiamis , Sasha N. Oster , Telesphor Kamgaing , Kenneth Shoemaker , Erich N. Ewy , Adel A. Elsherbini , Johanna M. Swan
Abstract: Embodiments include a waveguide bundle, a dielectric waveguide, and a vehicle. The waveguide bundle includes dielectric waveguides, where each dielectric waveguide has a dielectric core and a conductive coating around the dielectric core. The waveguide bundle also has a power delivery layer formed around the dielectric waveguides, and an insulating jacket enclosing the waveguide bundle. The waveguide bundle may also include the power deliver layer as a braided shield, where the braided shield provides at least one of a DC and an AC power line. The waveguide bundle may further have one of the dielectric waveguides provide a DC ground over their conductive coatings, where the AC power line does not use the braided shield as reference or ground. The waveguide bundle may include that the power delivery layer is separated from the dielectric waveguides by a braided shield, where the power delivery layer is a power delivery braided foil.
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公开(公告)号:US20150108660A1
公开(公告)日:2015-04-23
申请号:US14588183
申请日:2014-12-31
Applicant: Intel Corporation
Inventor: Pete Vogt , Andre Schaefer , Warren Morrow , John Halbert , Jin Kim , Kenneth Shoemaker
IPC: H01L25/065 , G11C5/06 , H01L27/108 , H01L23/48
CPC classification number: H01L25/0657 , G11C5/06 , H01L23/481 , H01L24/16 , H01L27/108 , H01L27/10882 , H01L27/10897 , H01L2224/16146 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541
Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.
Abstract translation: 具有提供偏移互连的接口的堆叠存储器。 存储器件的实施例包括与系统元件耦合的系统元件和存储器堆栈,存储器堆栈包括一个或多个存储器管芯层。 每个存储器管芯层包括第一面和第二面,每个存储管芯层的第二面包括用于将存储管芯层的数据接口引脚与耦合元件的第一面的数据接口引脚耦合的接口。 每个存储器管芯层的接口包括在存储管芯层的每个数据接口引脚和耦合元件的数据接口引脚的相应数据接口引脚之间提供偏移的连接。
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公开(公告)号:US11909841B2
公开(公告)日:2024-02-20
申请号:US16887087
申请日:2020-05-29
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Kshitij Arun Doshi , Kenneth Shoemaker , Vinodh Gopal , Ned M. Smith
CPC classification number: H04L67/56 , H04L47/805 , H04L49/109 , H04L49/3018 , H04L49/9068
Abstract: In one embodiment, a method includes: receiving, in an edge platform, a plurality of messages from a plurality of edge devices coupled to the edge platform, the plurality of messages comprising metadata including priority information and granularity information; extracting at least the priority information from the plurality of messages; storing the plurality of messages in entries of a pending request queue according to the priority information; selecting a first message stored in the pending request queue for delivery to a destination circuit; and sending a message header for the first message to the destination circuit via at least one interface circuit, the message header including the priority information, and thereafter sending a plurality of packets including payload information of the first message to the destination circuit via the at least one interface circuit. Other embodiments are described and claimed.
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公开(公告)号:US11594801B2
公开(公告)日:2023-02-28
申请号:US16613070
申请日:2017-07-01
Applicant: Intel Corporation
Inventor: Georgios Dogiamis , Sasha Oster , Telesphor Kamgaing , Erich Ewy , Kenneth Shoemaker , Adel Elsherbini , Johanna Swan
IPC: B60R11/04 , H01P3/16 , B60R16/023 , B60W40/02
Abstract: Embodiments of the invention include autonomous vehicles and mm-wave systems for communication between components. In an embodiment the vehicle includes an electronic control unit (ECU). The ECU may include a printed circuit board (PCB) and a CPU die packaged on a CPU packaging substrate. In an embodiment, the CPU packaging substrate is electrically coupled to the PCB. The ECU may also include an external predefined interface electrically coupled to the CPU die. In an embodiment, an active mm-wave interconnect may include a dielectric waveguide, and a first connector coupled to a first end of the dielectric waveguide. In an embodiment, the first connector comprises a first mm-wave engine, and the first connector is electrically coupled to the external predefined interface. Embodiments may also include a second connector coupled to a second end of the dielectric waveguide, wherein the second connector comprises a second mm-wave engine.
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公开(公告)号:US09768148B2
公开(公告)日:2017-09-19
申请号:US14588183
申请日:2014-12-31
Applicant: Intel Corporation
Inventor: Pete Vogt , Andre Schaefer , Warren Morrow , John Halbert , Jin Kim , Kenneth Shoemaker
IPC: G11C5/06 , H01L25/065 , H01L27/108 , H01L23/48 , H01L23/00
CPC classification number: H01L25/0657 , G11C5/06 , H01L23/481 , H01L24/16 , H01L27/108 , H01L27/10882 , H01L27/10897 , H01L2224/16146 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541
Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.
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