公开(公告)号：US09921640B2

公开(公告)日：2018-03-20

申请号：US13631092

申请日：2012-09-28

Applicant: INTEL CORPORATION

Inventor： Uwe Zillmann ,  Andre Schaefer ,  Ruchir Saraswat ,  Telesphor Kamgaing ,  Paul B. Fischer ,  Guido Droege

IPC: H01L23/48 ,  G06F1/32 ,  H05K1/02 ,  H05K1/16

CPC classification number: G06F1/3296 ,  H01L2924/0002 ,  H05K1/0262 ,  H05K1/165 ,  Y02D10/172 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Magnetically enhanced inductors integrated with microelectronic devices at chip-level. In embodiments, magnetically enhanced inductors include a through substrate vias (TSVs) with fill metal to carry an electrical current proximate to a magnetic layer disposed on a substrate through which the TSV passes. In certain magnetically enhanced inductor embodiments, a TSV fill metal is disposed within a magnetic material lining the TSV. In certain magnetically enhanced inductor embodiments, a magnetically enhanced inductor includes a plurality of interconnected TSVs disposed proximate to a magnetic material layer on a side of a substrate. In embodiments, voltage regulation circuitry disposed on a first side of a substrate is integrated with one or more magnetically enhanced inductors utilizing a TSV passing through the substrate. In further embodiments, integrated circuitry on a same substrate as the magnetically enhanced inductor, or on another substrate stacked thereon, completes the VR and/or is powered by the VR circuitry.

公开(公告)号：US09911689B2

公开(公告)日：2018-03-06

申请号：US15038623

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Kevin J. Lee ,  Ruchir Saraswat ,  Uwe Zillmann ,  Nicholas P. Cowley ,  Andre Schaefer ,  Rinkle Jain ,  Guido Droege

IPC: H01L21/48 ,  H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L25/065 ,  H01L23/48 ,  H01L21/822 ,  H01L23/492 ,  H01L23/498 ,  H01L27/06

CPC classification number: H01L23/5223 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/4875 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/492 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L25/0657 ,  H01L27/0629 ,  H01L28/90 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor provided using the disclosed techniques may include, for example, a conductive TBV surrounded by a dielectric material and an outer conductor plate. The TBV and outer plate can be formed, for example, so as to be self-aligned with one another in a coaxial arrangement, in accordance with some embodiments. The disclosed capacitor may extend through the body of a host die such that its terminals are accessible on the upper and/or lower surfaces thereof. Thus, in some cases, the host die can be electrically connected with another die to provide a die stack or other three-dimensional integrated circuit (3D IC), in accordance with some embodiments. In some instances, the disclosed capacitor can be utilized, for example, to provide integrated capacitance in a switched-capacitor voltage regulator (SCVR).

公开(公告)号：US09391453B2

公开(公告)日：2016-07-12

申请号：US13927227

申请日：2013-06-26

Applicant: Intel Corporation

Inventor： Guido Droege ,  Andre Schaefer ,  Uwe Zillmann

IPC: H02J1/00 ,  G11C7/00 ,  H02M1/088 ,  G11C5/14 ,  G11C5/02

CPC classification number: H02J1/00 ,  G05F1/618 ,  G11C5/025 ,  G11C5/14 ,  G11C5/147 ,  G11C7/00 ,  H01L2924/19042 ,  H01L2924/19104 ,  H02M1/088

Abstract: An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.

Abstract translation: 诸如异种装置的装置至少包括第一模具和第二模具。 该装置还包括第一电感元件，第二电感元件和开关控制电路。 开关控制电路设置在第一管芯中。 开关控制电路控制通过第一电感元件的电流以产生第一电压。 第一个电压为第一个模具供电。 第二电感元件耦合到第一电感元件。 第二电感元件产生第二电压以对第二管芯供电。 第一模具和第二模具可以根据不同的技术制造，并且其中第一模具和第二模具耐受不同的最大电压。 第一电压的大小可以大于第二电压的幅度。

公开(公告)号：US09361970B2

公开(公告)日：2016-06-07

申请号：US14327127

申请日：2014-07-09

Applicant: INTEL CORPORATION

Inventor： Andre Schaefer ,  John B. Halbert

IPC: G11C8/00 ,  G11C11/4074 ,  G11C8/14 ,  G11C11/408 ,  G11C8/08 ,  G11C11/404 ,  G06F1/32

CPC classification number: G11C11/4074 ,  G06F1/3275 ,  G11C8/08 ,  G11C8/14 ,  G11C11/4045 ,  G11C11/4085 ,  Y02D10/14

Abstract: Disclosed embodiments may include an apparatus having a segment wordline enable coupled to logic to selectively disable ones of a number of segment wordline drivers. The logic may partition a page of the apparatus to reduce power consumed through activation of the disabled ones of the number of segment wordlines. Other embodiments may be disclosed.

Abstract translation: 公开的实施例可以包括具有能够选择性地禁用多个段字线驱动器中的一个的逻辑的段字线的装置。 逻辑可以划分设备的页面，以通过激活段数字段线路中的禁用的一个来减少消耗的功率。 可以公开其他实施例。

公开(公告)号：US20150130534A1

公开(公告)日：2015-05-14

申请号：US14599245

申请日：2015-01-16

Applicant: Intel Corporation

Inventor： Guido Droege ,  Niklas Linkewitsch ,  Andre Schaefer

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L25/0657 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1057 ,  G11C7/1084 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/642 ,  H01L2223/6622 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.

Abstract translation: 一些实施例为3D堆叠模块提供电容AC耦合层间通信。

公开(公告)号：US10079489B2

公开(公告)日：2018-09-18

申请号：US15206999

申请日：2016-07-11

Applicant: Intel Corporation

Inventor： Guido Droege ,  Andre Schaefer ,  Uwe Zillmann

IPC: H02J1/00 ,  G11C7/00 ,  H02M1/088 ,  G11C5/14 ,  G11C5/02 ,  G05F1/618

CPC classification number: H02J1/00 ,  G05F1/618 ,  G11C5/025 ,  G11C5/14 ,  G11C5/147 ,  G11C7/00 ,  H01L2924/19042 ,  H01L2924/19104 ,  H02M1/088

Abstract: An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.

公开(公告)号：US09768148B2

公开(公告)日：2017-09-19

申请号：US14588183

申请日：2014-12-31

Applicant: Intel Corporation

Inventor： Pete Vogt ,  Andre Schaefer ,  Warren Morrow ,  John Halbert ,  Jin Kim ,  Kenneth Shoemaker

IPC: G11C5/06 ,  H01L25/065 ,  H01L27/108 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  G11C5/06 ,  H01L23/481 ,  H01L24/16 ,  H01L27/108 ,  H01L27/10882 ,  H01L27/10897 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541

Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

公开(公告)号：US10853216B2

公开(公告)日：2020-12-01

申请号：US14739941

申请日：2015-06-15

Applicant: INTEL CORPORATION

Inventor： Tsun Ho Liu ,  Andre Schaefer ,  Hoi M. Ng ,  Guy R. Murray ,  Oleg Mikulchenko ,  Xiaofang Gao

IPC: G06F11/30 ,  G11C11/4096 ,  G11C11/406 ,  G06F11/34 ,  G06F1/3234

Abstract: A mechanism is described for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems according to one embodiment of the invention. A method of embodiments of the invention includes monitoring movements of a valid data eye associated with a memory device of a plurality of memory devices of a memory system at a computing system. The monitoring may include initiating write commands during one or more refresh periods associated with the valid data eye. The method may include determining drifting in the movement of the data eye, and correcting the drifting based on adjusting one or more existing phase interpolator values associated with the movements of the data eye.

公开(公告)号：US09287196B2

公开(公告)日：2016-03-15

申请号：US13730331

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Ruchir Saraswat ,  Uwe Zillmann ,  Andre Schaefer ,  Tor Lund-Larsen

IPC: H01L27/08 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065 ,  H01L27/06 ,  H01L23/64

CPC classification number: H01L23/481 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2223/6616 ,  H01L2223/6666 ,  H01L2223/6672 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Resonant clocking for three-dimensional stacked devices. An embodiment of an apparatus includes a stack including integrated circuit dies; and through silicon vias through at least one of the dies, wherein at least a first through silicon via of the through silicon vias includes a capacitive structure or an inductive structure, the first through silicon via being formed in a first die of the plurality of dies. The apparatus includes a resonant circuit, the first through silicon via used as a first circuit element of the resonant circuit.

Abstract translation: 谐振时钟三维堆叠器件。 装置的实施例包括：堆叠，其包括集成电路管芯; 并且通过至少一个管芯的硅通孔，其中穿过硅通孔的至少第一通孔硅通道包括电容结构或电感结构，所述第一穿硅通孔形成在所述多个管芯的第一管芯中 。 该装置包括谐振电路，第一通孔硅用作谐振电路的第一电路元件。

公开(公告)号：US20170011779A1

公开(公告)日：2017-01-12

申请号：US15206999

申请日：2016-07-11

Applicant: Intel Corporation

Inventor： Guido Droege ,  Andre Schaefer ,  Uwe Zillmann

IPC: G11C5/14

CPC classification number: H02J1/00 ,  G05F1/618 ,  G11C5/025 ,  G11C5/14 ,  G11C5/147 ,  G11C7/00 ,  H01L2924/19042 ,  H01L2924/19104 ,  H02M1/088

Abstract: An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.

Abstract translation: 诸如异种装置的装置至少包括第一模具和第二模具。 该装置还包括第一电感元件，第二电感元件和开关控制电路。 开关控制电路设置在第一管芯中。 开关控制电路控制通过第一电感元件的电流以产生第一电压。 第一个电压为第一个模具供电。 第二电感元件耦合到第一电感元件。 第二电感元件产生第二电压以对第二管芯供电。 第一模具和第二模具可以根据不同的技术制造，并且其中第一模具和第二模具耐受不同的最大电压。 第一电压的大小可以大于第二电压的幅度。