公开(公告)号：US12164322B2

公开(公告)日：2024-12-10

申请号：US17359413

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Amit K. Jain ,  Mauricio Aguilar Salas ,  Jonathan Douglas ,  Anant Deval

IPC: G05F1/59 ,  G05F1/575 ,  G06F1/3203

Abstract: Techniques and mechanisms for determining an operational mode of a voltage regulator. In an embodiment, an integrated circuit (IC) die is coupled to receive power from a voltage regulator (VR) via a power delivery network (PDN) which comprises circuitry in or on a substrate, such as that of a printed circuit board. The IC die receives from the substrate information indicating a characteristic of a parasitic impedance at the substrate. Based on the information, a controller unit at the IC die selects one of multiple VR modes which each correspond to a respective one of different parasitic impedance characteristics. The controller then signals the VR to provide the selected mode. In an embodiment one of the VR modes corresponds to a relatively high impedance, and also corresponds to a relatively stable sensitivity function in a frequency range above a control bandwidth.

公开(公告)号：US20180046241A1

公开(公告)日：2018-02-15

申请号：US15800144

申请日：2017-11-01

Applicant: Intel Corporation

Inventor： Stephen H. Gunther ,  Edward A. Burton ,  Anant Deval ,  Stephan Jourdan ,  Robert Greiner ,  Michael Cornaby

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

公开(公告)号：US20180232039A1

公开(公告)日：2018-08-16

申请号：US15951290

申请日：2018-04-12

Applicant: Intel Corporation

Inventor： Stephen H. Gunther ,  Edward A. Burton ,  Anant Deval ,  Stephan Jourdan ,  Robert Greiner ,  Michael Cornaby

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

公开(公告)号：US09841803B2

公开(公告)日：2017-12-12

申请号：US14689175

申请日：2015-04-17

Applicant: Intel Corporation

Inventor： Stephen H. Gunther ,  Edward A. Burton ,  Anant Deval ,  Stephan Jourdan ,  Robert Greiner ,  Michael Cornaby

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

公开(公告)号：US09712167B2

公开(公告)日：2017-07-18

申请号：US14582867

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Hong Yun Tan ,  Anant Deval ,  R. Kenneth Hose

IPC: H03K19/003 ,  G06F1/16 ,  H03K17/16 ,  H03K17/30 ,  H03K19/00 ,  G06F1/20 ,  H03K19/0948

CPC classification number: H03K19/00315 ,  G06F1/16 ,  G06F1/20 ,  H03K17/163 ,  H03K17/302 ,  H03K19/0016 ,  H03K19/0948

Abstract: Described is an apparatus which comprises: a first node to provide an un-gated power supply; a second node to provide a threshold dependent supply; an inverter with an input and an output, the inverter coupled to the first and second nodes, the inverter to receive the un-gated power supply at its power supply node, and to receive the threshold dependent supply for supplying ground supply at its ground node; and a transistor with its gate terminal coupled to the output of the inverter, the transistor to provide gated power supply to one or more logic units.

公开(公告)号：US20220413536A1

公开(公告)日：2022-12-29

申请号：US17359413

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Amit K. Jain ,  Mauricio Aguilar Salas ,  Jonathan Douglas ,  Anant Deval

IPC: G05F1/59 ,  G06F1/3203 ,  G05F1/575

Abstract: Techniques and mechanisms for determining an operational mode of a voltage regulator. In an embodiment, an integrated circuit (IC) die is coupled to receive power from a voltage regulator (VR) via a power delivery network (PDN) which comprises circuitry in or on a substrate, such as that of a printed circuit board. The IC die receives from the substrate information indicating a characteristic of a parasitic impedance at the substrate. Based on the information, a controller unit at the IC die selects one of multiple VR modes which each correspond to a respective one of different parasitic impedance characteristics. The controller then signals the VR to provide the selected mode. In an embodiment one of the VR modes corresponds to a relatively high impedance, and also corresponds to a relatively stable sensitivity function in a frequency range above a control bandwidth.

公开(公告)号：US20180232041A1

公开(公告)日：2018-08-16

申请号：US15951310

申请日：2018-04-12

Applicant: Intel Corporation

Inventor： Stephen H. Gunther ,  Edward A. Burton ,  Anant Deval ,  Stephan Jourdan ,  Robert Greiner ,  Michael Cornaby

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

公开(公告)号：US20180232040A1

公开(公告)日：2018-08-16

申请号：US15951299

申请日：2018-04-12

Applicant: Intel Corporation

Inventor： Stephen H. Gunther ,  Edward A. Burton ,  Anant Deval ,  Stephan Jourdan ,  Robert Greiner ,  Michael Cornaby

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

公开(公告)号：US20160239036A1

公开(公告)日：2016-08-18

申请号：US14621261

申请日：2015-02-12

Applicant: Intel Corporation

Inventor： Fabrice Paillet ,  Gerhard Schrom ,  Anant Deval ,  Rajan Vijayaraghavan

IPC: G05F3/08 ,  G06F1/26 ,  H02M1/08 ,  H03K3/011 ,  H02M3/158

CPC classification number: G05F3/08 ,  G05F1/46 ,  G06F1/26 ,  H02M3/1584 ,  H02M2001/0045 ,  H02M2001/007 ,  H02M2001/008

Abstract: The present disclosure provides a power delivery scheme to provide a parallel regulation feature for integrated voltage regulators (IVRs).

Abstract translation: 本公开提供了为集成稳压器（IVR）提供并行调节特征的功率传递方案。

公开(公告)号：US11429173B2

公开(公告)日：2022-08-30

申请号：US16230440

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  Amit Jain ,  Anant Deval ,  Nimrod Angel ,  Fabrice Paillet ,  Michael Zelikson ,  Sergio Carlo Rodriguez

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3206 ,  H02M3/158 ,  H02M1/08 ,  G06F1/20 ,  G06F1/3296 ,  H02M1/32 ,  G06F1/324 ,  H02M1/00 ,  H02M3/156

Abstract: Described is an apparatus and method to prevent a processor from abruptly shutting down by proactive power management. The apparatus comprises a power supply rail to receive a current and a voltage from a power supply generator (e.g., a DC-DC converter, and low dropout regulator); a processor coupled to the power supply rail, wherein the processor is to operate with a current and a voltage provided by the power supply rail; and an interface to receive a request to throttle one or more performance parameters of the processor when a monitored current through the power supply rail or a monitored voltage on the power supply rail crosses a threshold current or a threshold voltage, respectively, wherein the threshold current is below a catastrophic threshold current of a voltage regulator, or wherein the threshold voltage is above a catastrophic threshold voltage of the processor.