公开(公告)号：US20200235243A1

公开(公告)日：2020-07-23

申请号：US16640043

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Uygar E. Avci ,  Joshua M. Howard ,  Seiyon Kim ,  Ian A. Young

IPC: H01L29/78 ,  H01L49/02 ,  H01L29/51

Abstract: Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.

公开(公告)号：US11004868B2

公开(公告)日：2021-05-11

申请号：US16487417

申请日：2017-03-22

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Uygar E. Avci ,  Joshua M. Howard ,  Ian A. Young ,  Daniel H. Morris

IPC: H01L29/78 ,  H01L27/1159 ,  H01L21/28 ,  H01L27/11592 ,  H01L29/51

Abstract: Memory field-effect transistors and methods of manufacturing the same are disclosed. An example apparatus includes a semiconductor substrate and a ferroelectric gate insulator of a memory field-effect transistor formed within a trench having walls defined by spacers and a base defined by the semiconductor substrate. The apparatus further includes a gate conductor formed on the ferroelectric gate insulator. The ferroelectric gate insulator is to separate a bottom surface of the gate conductor and the substrate.

公开(公告)号：US20220123151A1

公开(公告)日：2022-04-21

申请号：US17551899

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Joshua M. Howard ,  Seiyon Kim ,  Ian A. Young

IPC: H01L29/78 ,  H01L49/02 ,  H01L29/51

Abstract: Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an insulating material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.

公开(公告)号：US11239361B2

公开(公告)日：2022-02-01

申请号：US16640043

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Uygar E. Avci ,  Joshua M. Howard ,  Seiyon Kim ,  Ian A. Young

IPC: H01L29/78 ,  H01L49/02 ,  H01L29/51

Abstract: Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an insulating material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.

公开(公告)号：US11799029B2

公开(公告)日：2023-10-24

申请号：US17551899

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Joshua M. Howard ,  Seiyon Kim ,  Ian A. Young

IPC: H01L29/78 ,  H01L29/51 ,  H10B51/30 ,  H10B53/30 ,  H01L49/02

CPC classification number: H01L29/78391 ,  H01L28/56 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/785 ,  H10B51/30 ,  H10B53/30

Abstract: Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an insulating material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.

公开(公告)号：US11735652B2

公开(公告)日：2023-08-22

申请号：US16635739

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Uygar E. Avci ,  Joshua M. Howard ,  Ian A. Young ,  Daniel H. Morris

IPC: H01L29/66 ,  H01L29/51

CPC classification number: H01L29/6684 ,  H01L29/516

Abstract: Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.