公开(公告)号：US20240321987A1

公开(公告)日：2024-09-26

申请号：US18187990

申请日：2023-03-22

Applicant: Intel Corporation

Inventor： Tao Chu ,  Guowei Xu ,  Robin Chao ,  Chiao-Ti Huang ,  Feng Zhang ,  Minwoo Jang ,  Chia-Ching Lin ,  Biswajeet Guha ,  Yue Zhong ,  Anand S. Murthy

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Described herein are integrated circuit devices that include both nanoribbon-based transistors and fin-shaped transistors. The nanoribbon transistors may have shorter channel lengths than the fin transistors. In addition, the nanoribbon transistors may have thinner gate dielectrics than the fin transistors.

公开(公告)号：US20230371233A1

公开(公告)日：2023-11-16

申请号：US17742628

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Travis W. Lajoie ,  Forough Mahmoudabadi ,  Shailesh Kumar Madisetti ,  Van H. Le ,  Timothy Jen ,  Cheng Tan ,  Jisoo Kim ,  Miriam R. Reshotko ,  Vishak Venkatraman ,  Eva Vo ,  Yue Zhong ,  Yu-Che Chiu ,  Moshe Dolejsi ,  Lorenzo Ferrari ,  Akash Kannegulla ,  Deepyanti Taneja ,  Mark Armstrong ,  Kamal H. Baloch ,  Afrin Sultana ,  Albert B. Chen ,  Vamsi Evani ,  Yang Yang ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/786 ,  H01L29/94

CPC classification number: H01L27/10805 ,  H01L23/5283 ,  H01L29/78696 ,  H01L29/94

Abstract: Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.