公开(公告)号：US10579125B2

公开(公告)日：2020-03-03

申请号：US15055578

申请日：2016-02-27

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Pavithra Sampath ,  Kirk Pfaender ,  Kahraman D. Akdemir ,  Ariel Gur

IPC: G06F1/324 ,  G06F9/30

Abstract: An integrated circuit of an aspect includes a power control unit having an interface to receive an indication that one or more instructions of a first type are to be performed by a core. The power control unit also has logic to control a maximum clock frequency for the core based on the indication that the instructions of the first type are to be performed by the core.

公开(公告)号：US11216409B2

公开(公告)日：2022-01-04

申请号：US17025992

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Kirk Pfaender

IPC: G06F15/78 ,  G06F1/18 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/26 ,  G06F9/4401

Abstract: Apparatuses, methods and storage medium for providing access from outside a multicore processor System on Chip (SoC) are disclosed herein. In embodiments, an SoC may include a memory to store a plurality of embedded values correspondingly associated with a plurality of architecturally identical cores. Each embedded value may indicate a default voltage for a respective one of the plurality of architecturally identical cores. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to provide access from outside the multicore processor SoC to individually configure voltages of the plurality of architecturally identical cores to values that are different than the values of the default voltages. Other embodiments may be described and/or claimed.

公开(公告)号：US10013392B2

公开(公告)日：2018-07-03

申请号：US15007021

申请日：2016-01-26

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Kirk Pfaender

IPC: G06F15/78 ,  G06F1/18 ,  G06F1/32 ,  G06F1/26 ,  G06F9/4401

CPC classification number: G06F15/7807 ,  G06F1/189 ,  G06F1/26 ,  G06F1/266 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/4403 ,  G06F9/4405 ,  Y02D10/152 ,  Y02D10/172

Abstract: Apparatuses, methods and storage medium for providing access from outside a multicore processor System on Chip (SoC) are disclosed herein. In embodiments, an SoC may include a memory to store a plurality of embedded values correspondingly associated with a plurality of architecturally identical cores. Each embedded value may indicate a default voltage for a respective one of the plurality of architecturally identical cores. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to provide access from outside the multicore processor SoC to individually configure voltages of the plurality of architecturally identical cores to values that are different than the values of the default voltages. Other embodiments may be described and/or claimed.

公开(公告)号：US11892969B2

公开(公告)日：2024-02-06

申请号：US17556755

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Kirk Pfaender

IPC: G06F15/78 ,  G06F1/18 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/26 ,  G06F9/4401

CPC classification number: G06F15/7807 ,  G06F1/189 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3296 ,  G06F1/26 ,  G06F1/266 ,  G06F9/4403 ,  G06F9/4405 ,  Y02D10/00

Abstract: Apparatuses, methods and storage medium for providing access from outside a multicore processor System on Chip (SoC) are disclosed herein. In embodiments, an SoC may include a memory to store a plurality of embedded values correspondingly associated with a plurality of architecturally identical cores. Each embedded value may indicate a default voltage for a respective one of the plurality of architecturally identical cores. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to provide access from outside the multicore processor SoC to individually configure voltages of the plurality of architecturally identical cores to values that are different than the values of the default voltages. Other embodiments may be described and/or claimed.

公开(公告)号：US10783110B2

公开(公告)日：2020-09-22

申请号：US16026691

申请日：2018-07-03

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Kirk Pfaender

IPC: G06F15/78 ,  G06F1/18 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/26 ,  G06F9/4401

Abstract: Apparatuses, methods and storage medium for providing access from outside a multicore processor System on Chip (SoC) are disclosed herein. In embodiments, an SoC may include a memory to store a plurality of embedded values correspondingly associated with a plurality of architecturally identical cores. Each embedded value may indicate a default voltage for a respective one of the plurality of architecturally identical cores. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to provide access from outside the multicore processor SoC to individually configure voltages of the plurality of architecturally identical cores to values that are different than the values of the default voltages. Other embodiments may be described and/or claimed.