公开(公告)号：US11579944B2

公开(公告)日：2023-02-14

申请号：US16190806

申请日：2018-11-14

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F9/50 ,  G06F9/52 ,  G06F13/20 ,  G06F1/28 ,  G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  G06F1/3287

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

公开(公告)号：US20190079806A1

公开(公告)日：2019-03-14

申请号：US16190806

申请日：2018-11-14

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F9/52 ,  G06F13/20 ,  G06F9/50 ,  G06F1/28

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

公开(公告)号：US11953962B2

公开(公告)日：2024-04-09

申请号：US18086799

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F9/50 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/52 ,  G06F13/20 ,  G06F1/3287 ,  G06F1/3296

CPC classification number: G06F1/3203 ,  G06F1/28 ,  G06F1/324 ,  G06F9/5044 ,  G06F9/5094 ,  G06F9/52 ,  G06F13/20 ,  G06F1/3287 ,  G06F1/3296

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

公开(公告)号：US20210036708A1

公开(公告)日：2021-02-04

申请号：US16528435

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Ariel Gur ,  Daniel J. Ragland ,  Yoav Ben-Raphael ,  Ernest Knoll

IPC: H03L7/18 ,  H03L7/187 ,  H03L7/14

Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.

公开(公告)号：US10958278B2

公开(公告)日：2021-03-23

申请号：US16528435

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Ariel Gur ,  Daniel J. Ragland ,  Yoav Ben-Raphael ,  Ernest Knoll

IPC: H03D3/24 ,  H03L7/18 ,  H03L7/14 ,  H03L7/187

Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.

公开(公告)号：US10095302B2

公开(公告)日：2018-10-09

申请号：US15250123

申请日：2016-08-29

Applicant: Intel Corporation

Inventor： Ariel Gur ,  Daniel J Ragland ,  Ofer Nathan ,  Nadav Shulman ,  Esfir Natanzon

IPC: G06F1/32

Abstract: A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.

公开(公告)号：US11899599B2

公开(公告)日：2024-02-13

申请号：US17527929

申请日：2021-11-16

Applicant: INTEL CORPORATION

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Doron Rajwan ,  Hisham Abu Salah ,  Ariel Gur ,  Guy M. Therien ,  Russell J. Fenger

IPC: G06F13/24 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30 ,  G06F1/3234 ,  G06F9/44 ,  G06F9/4401

CPC classification number: G06F13/24 ,  G06F1/329 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/44 ,  G06F9/4411

Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

公开(公告)号：US11182315B2

公开(公告)日：2021-11-23

申请号：US15430345

申请日：2017-02-10

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Doron Rajwan ,  Hisham Abu Salah ,  Ariel Gur ,  Guy M. Therien ,  Russell J. Fenger

IPC: G06F13/24 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30 ,  G06F9/44 ,  G06F9/4401 ,  G06F1/3234

Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

公开(公告)号：US20230131521A1

公开(公告)日：2023-04-27

申请号：US18086799

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F1/3203 ,  G06F9/50 ,  G06F1/324

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

公开(公告)号：US10579125B2

公开(公告)日：2020-03-03

申请号：US15055578

申请日：2016-02-27

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Pavithra Sampath ,  Kirk Pfaender ,  Kahraman D. Akdemir ,  Ariel Gur

IPC: G06F1/324 ,  G06F9/30

Abstract: An integrated circuit of an aspect includes a power control unit having an interface to receive an indication that one or more instructions of a first type are to be performed by a core. The power control unit also has logic to control a maximum clock frequency for the core based on the indication that the instructions of the first type are to be performed by the core.