公开(公告)号：US09817714B2

公开(公告)日：2017-11-14

申请号：US14998142

申请日：2015-12-26

申请人： Intel Corporation

发明人： John B Halbert ,  Kuljit S Bains ,  Kjersten E Criss

IPC分类号： G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  H03M13/09 ,  H03M13/00 ,  G11C29/42 ,  G11C11/401

CPC分类号： G06F11/1048 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/401 ,  G11C29/42 ,  G11C29/52 ,  H03M13/095 ,  H03M13/6566

摘要： In a system where a memory device performs on-die ECC, the ECC operates on N-bit data words as two (N/2)-bit segments, with a code matrix having a corresponding N codes that can be operated on as a first portion of (N/2) codes and a second portion of (N/2) codes to compute first and second error checks for first and second (N/2)-bit segments of the data word, respectively. In the code matrix, a bitwise XOR of any two codes in the first portion of the code matrix or any two codes in the second portion of the code matrix results in a code that is either not in the code matrix or is in the other portion of the code matrix. Thus, a miscorrected double bit error in one portion causes a bit to be toggled in the other portion instead of creating a triple bit error.