公开(公告)号：US10127101B2

公开(公告)日：2018-11-13

申请号：US14998184

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： John B Halbert ,  Kuljit S Bains

IPC: H03M13/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  H03M13/09 ,  G11C29/42 ,  G11C11/401

Abstract: An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

公开(公告)号：US09811420B2

公开(公告)日：2017-11-07

申请号：US14670413

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Debaleena Das ,  Bill Nale ,  Kuljit S Bains ,  John B Halbert

IPC: G06F11/00 ,  G06F11/10

CPC classification number: G06F11/1048 ,  G06F11/00 ,  G06F11/1008 ,  G06F11/1076 ,  G06F11/1084

Abstract: Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

公开(公告)号：US09740558B2

公开(公告)日：2017-08-22

申请号：US14865956

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： John B Halbert ,  Kuljit S Bains

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  G11C29/42 ,  G11C29/44 ,  G11C11/40 ,  G11C29/56 ,  G11C29/04

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C11/40 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C29/56008 ,  G11C2029/0411

Abstract: A memory subsystem enables managing error correction information. A memory device internally performs error detection for a range of memory locations, and increments an internal count for each error detected. The memory device includes ECC logic to generate an error result indicating a difference between the internal count and a baseline number of errors preset for the memory device. The memory device can provide the error result to an associated host of the system to expose only a number of errors accumulated without exposing internal errors from prior to incorporation into a system. The memory device can be made capable to generate internal addresses to execute commands received from the memory controller. The memory device can be made capable to reset the counter after a first pass through the memory area in which errors are counted.

公开(公告)号：US09747971B2

公开(公告)日：2017-08-29

申请号：US14955012

申请日：2015-11-30

Applicant: Intel Corporation

Inventor： Kuljit S Bains ,  John B Halbert ,  Christopher P Mozak ,  Theodore Z Schoenborn ,  Zvika Greenfield

IPC: G06F12/10 ,  G11C11/406 ,  G11C11/4091

CPC classification number: G11C11/4091 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/7211 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

公开(公告)号：US20160225433A1

公开(公告)日：2016-08-04

申请号：US14955012

申请日：2015-11-30

Applicant: Intel Corporation

Inventor： Kuljit S Bains ,  John B Halbert ,  Christopher P Mozak ,  Theodore Z Schoenborn ,  Zvika Greenfield

IPC: G11C11/406 ,  G11C11/4091

CPC classification number: G11C11/4091 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/7211 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract translation: 内存控制器发出目标刷新命令。 存储器件的特定行可以是重复访问的目标。 当行在时间阈值（也称为“锤击”或“行锤事件”）中被重复访问时，物理上相邻的行（“受害者”行）可能经历数据损坏。 存储器控制器接收行敲击事件的指示，识别与行锤事件相关联的行，并且将一个或多个命令发送到存储器设备，以使存储器设备执行将刷新受害者行的目标刷新。

公开(公告)号：US09842021B2

公开(公告)日：2017-12-12

申请号：US14998059

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： John B Halbert ,  Kuljit S Bains

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  H03M13/09 ,  H03M13/00 ,  G11C29/42 ,  G11C11/401

CPC classification number: G06F11/1048 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/401 ,  G11C29/42 ,  G11C29/52 ,  H03M13/095 ,  H03M13/6566

Abstract: A check bit read mode enables a memory device to provide internal check bits to an associated host. A memory controller of a memory subsystem can generate one or more read commands for memory devices of the memory subsystem. The read command can include address location information. The memory devices include memory arrays with memory locations addressable with the address location information. The memory locations have associated data and internal check bits, where the check bits are generated internally by the memory for error correction. If the memory device is configured for check bit read mode, in response to the read command, it sends the internal check bits associated with the identified address location. If the memory device is not configured check bit read mode, it returns the data in response to the read command without exposing the internal check bits.

公开(公告)号：US09384821B2

公开(公告)日：2016-07-05

申请号：US14108830

申请日：2013-12-17

Applicant: Intel Corporation

Inventor： Kuljit S Bains ,  John B Halbert

IPC: G06F12/00 ,  G11C11/4078 ,  G06F13/16 ,  G11C11/406 ,  G11C11/408 ,  G11C29/50 ,  G11C29/04

CPC classification number: G11C11/4078 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/0409

Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to it row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

Abstract translation: 存储器子系统的检测逻辑获得存储器设备的阈值，该存储器设备指示在时间窗口内的数量的访问，导致物理上相邻的行上的数据损坏风险。 检测逻辑从存储器件的配置信息的寄存器获得阈值，并且可以是存储器件本身的寄存器和/或可以是存储器件所属的存储器模块的配置存储设备的条目 。 检测逻辑确定存储器件的行的访问次数是否超过阈值。 响应于检测到的访问次数超过阈值，检测逻辑可以产生触发以使存储器件执行针对物理上相邻的受害者行的刷新。

公开(公告)号：US09817714B2

公开(公告)日：2017-11-14

申请号：US14998142

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： John B Halbert ,  Kuljit S Bains ,  Kjersten E Criss

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  H03M13/09 ,  H03M13/00 ,  G11C29/42 ,  G11C11/401

CPC classification number: G06F11/1048 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/401 ,  G11C29/42 ,  G11C29/52 ,  H03M13/095 ,  H03M13/6566

Abstract: In a system where a memory device performs on-die ECC, the ECC operates on N-bit data words as two (N/2)-bit segments, with a code matrix having a corresponding N codes that can be operated on as a first portion of (N/2) codes and a second portion of (N/2) codes to compute first and second error checks for first and second (N/2)-bit segments of the data word, respectively. In the code matrix, a bitwise XOR of any two codes in the first portion of the code matrix or any two codes in the second portion of the code matrix results in a code that is either not in the code matrix or is in the other portion of the code matrix. Thus, a miscorrected double bit error in one portion causes a bit to be toggled in the other portion instead of creating a triple bit error.

公开(公告)号：US09728245B2

公开(公告)日：2017-08-08

申请号：US14865754

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kuljit S Bains ,  John B Halbert ,  Nadav Bonen ,  Tomer Levy

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40618 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4087

Abstract: Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.

公开(公告)号：US09721643B2

公开(公告)日：2017-08-01

申请号：US15170606

申请日：2016-06-01

Applicant: Intel Corporation

Inventor： Kuljit S Bains ,  John B Halbert

IPC: G06F12/12 ,  G11C11/4078 ,  G06F13/16 ,  G11C11/406 ,  G11C11/408 ,  G11C29/50 ,  G11C29/04

CPC classification number: G11C11/4078 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/0409

Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.