公开(公告)号：US20180286876A1

公开(公告)日：2018-10-04

申请号：US15477040

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Changhan Kim ,  Kunal Shrotri ,  John Hopkins ,  Darwin Franseda Fan

IPC: H01L27/11524 ,  H01L29/66 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/423 ,  H01L27/12

CPC classification number: H01L27/11524 ,  H01L27/1157 ,  H01L27/1203 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of insulative layers vertically spaced apart from one another. The memory component can also include a vertically oriented conductive channel extending through the plurality of insulative layers. In addition, the memory component can include a charge storage structure disposed between adjacent insulative layers. The charge storage structure can have a vertical cross section with a first side oriented toward the conductive channel and a second side opposite the first side. A length of the first side can be greater than a length of the second side. In another example, the vertical cross-section of the charge storage structure comprises a non-rectangular shape, such as a trapezoid shape. Associated systems and methods are also disclosed.

公开(公告)号：US10269824B2

公开(公告)日：2019-04-23

申请号：US15477051

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Changhan Kim ,  Scott M. Pook

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L21/02 ,  G11C16/10 ,  G11C16/04

Abstract: Conductive channel technology is disclosed. In one example, a memory component can include a source line, a conductive channel having first and second conductive layers electrically coupled to the source line and memory cells adjacent to the conductive channel. In one aspect, channel conductivity and reliability is improved over a single layer conductive channel formation scheme by preventing unwanted oxide formation, increasing the interface contact area, and by modulating material grain size and boundaries via multiple thin channel integration scheme. Associated systems and methods are also disclosed.

公开(公告)号：US10217755B2

公开(公告)日：2019-02-26

申请号：US15477040

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Changhan Kim ,  Kunal Shrotri ,  John Hopkins ,  Darwin Franseda Fan

IPC: G11C16/04 ,  H01L27/11524 ,  H01L29/66 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/423 ,  H01L27/12

Abstract: Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of insulative layers vertically spaced apart from one another. The memory component can also include a vertically oriented conductive channel extending through the plurality of insulative layers. In addition, the memory component can include a charge storage structure disposed between adjacent insulative layers. The charge storage structure can have a vertical cross section with a first side oriented toward the conductive channel and a second side opposite the first side. A length of the first side can be greater than a length of the second side. In another example, the vertical cross-section of the charge storage structure comprises a non-rectangular shape, such as a trapezoid shape. Associated systems and methods are also disclosed.

公开(公告)号：US20180286874A1

公开(公告)日：2018-10-04

申请号：US15477051

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Changhan Kim ,  Scott M. Pook

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11543 ,  H01L21/02 ,  H01L29/68 ,  G11C16/10 ,  G11C16/04

CPC classification number: H01L27/1157 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/02587 ,  H01L27/11582

Abstract: Conductive channel technology is disclosed. In one example, a memory component can include a source line, a conductive channel having first and second conductive layers electrically coupled to the source line and memory cells adjacent to the conductive channel. In one aspect, channel conductivity and reliability is improved over a single layer conductive channel formation scheme by preventing unwanted oxide formation, increasing the interface contact area, and by modulating material grain size and boundaries via multiple thin channel integration scheme. Associated systems and methods are also disclosed.