公开(公告)号：US09379321B1

公开(公告)日：2016-06-28

申请号：US14664745

申请日：2015-03-20

Applicant: Intel Corporation

Inventor： Kuo-Wei Chang ,  Paolo Fantini

IPC: H01L45/00 ,  H01L27/24 ,  C03C3/00 ,  C03C3/04 ,  C03C3/062 ,  C03C3/32

CPC classification number: H01L45/143 ,  C03C3/00 ,  C03C3/04 ,  C03C3/062 ,  C03C3/32 ,  C03C3/321 ,  H01L27/2409 ,  H01L45/00 ,  H01L45/04 ,  H01L45/06 ,  H01L45/14 ,  H01L45/141

Abstract: Embodiments of the present disclosure describe chalcogenide glass compositions and chalcogenide switch devices (CSD.) The compositions generally may include 3% to 15%, silicon, 8% to 16% germanium in, greater than 45% selenium, and 20% to 35% arsenic, by weight. The amount of silicon and germanium in a composition generally may include more than 10% by weight. CSDs may include various compositions of chalcogenide glass, and a plurality of them may be used in a memory device, such as die with a memory component, and may be used in various electronic components and systems. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施方案描述了硫族化物玻璃组合物和硫族化物开关装置（CSD。）组合物通常可以包括3％至15％的硅，8％至16％的锗，大于45％的硒和20％至35％ 砷，重量。 组合物中硅和锗的量通常可以包括大于10重量％。 CSD可以包括硫族化物玻璃的各种组合物，并且它们中的多个可以用于诸如具有存储器组件的管芯的存储器件中，并且可以用于各种电子部件和系统中。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20190044062A1

公开(公告)日：2019-02-07

申请号：US15853697

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Paolo Fantini

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/1233 ,  B82Y35/00 ,  B82Y40/00 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76 ,  H01L27/2427 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/146 ,  H01L45/149 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1625

Abstract: A variable resistance memory cell with a wide difference (“window”) between threshold voltages is provided. The window between threshold voltages is increased by amplifying the stoichiometry gradient by means of an asymmetry in the memory cell architecture to provide a greater margin for detecting different logic states of the memory cell.

公开(公告)号：US10475995B2

公开(公告)日：2019-11-12

申请号：US15853697

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Paolo Fantini

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24 ,  B82Y40/00 ,  B82Y35/00

Abstract: A variable resistance memory cell with a wide difference (“window”) between threshold voltages is provided. The window between threshold voltages is increased by amplifying the stoichiometry gradient by means of an asymmetry in the memory cell architecture to provide a greater margin for detecting different logic states of the memory cell.