公开(公告)号：US20190188136A1

公开(公告)日：2019-06-20

申请号：US16281941

申请日：2019-02-21

申请人： Intel Corporation

发明人： Pinkesh Shah ,  Herbert Hum ,  Lingdan Zeng

IPC分类号： G06F12/084 ,  G06F13/28 ,  G06F12/122

CPC分类号： G06F12/084 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/601 ,  G06F2212/6042

摘要： A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.

公开(公告)号：US20230004430A1

公开(公告)日：2023-01-05

申请号：US17856968

申请日：2022-07-02

申请人： Intel Corporation

发明人： Richard Richmond ,  Eric Luk ,  Lingdan Zeng ,  Lance Hacking ,  Alessandro Palla ,  Mohamed Elmalaki ,  Sara Almalih

IPC分类号： G06F9/48 ,  G06N3/10

摘要： Technology for estimating neural network (NN) power profiles includes obtaining a plurality of workloads for a compiled NN model, the plurality of workloads determined for a hardware execution device, determining a hardware efficiency factor for the compiled NN model, and generating, based on the hardware efficiency factor, a power profile for the compiled NN model on one or more of a per-layer basis or a per-workload basis. The hardware efficiency factor can be determined on based on a hardware efficiency measurement and a hardware utilization measurement, and can be determined on a per-workload basis. A configuration file can be provided for generating the power profile, and an output visualization of the power profile can be generated. Further, feedback information can be generated to perform one or more of selecting a hardware device, optimizing a breakdown of workloads, optimizing a scheduling of tasks, or confirming a hardware device design.

公开(公告)号：US09880935B2

公开(公告)日：2018-01-30

申请号：US14222792

申请日：2014-03-24

申请人： Intel Corporation

发明人： Pinkesh Shah ,  Herbert Hum ,  Lingdan Zeng

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F13/28 ,  G06F12/084 ,  G06F12/122

CPC分类号： G06F12/084 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/601 ,  G06F2212/6042

摘要： A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.

公开(公告)号：US10248568B2

公开(公告)日：2019-04-02

申请号：US15879030

申请日：2018-01-24

申请人： Intel Corporation

发明人： Pinkesh Shah ,  Herbert Hum ,  Lingdan Zeng

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F13/28 ,  G06F12/084 ,  G06F12/122

摘要： A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.

公开(公告)号：US20180165193A1

公开(公告)日：2018-06-14

申请号：US15879030

申请日：2018-01-24

申请人： Intel Corporation

发明人： Pinkesh Shah ,  Herbert Hum ,  Lingdan Zeng

IPC分类号： G06F12/084 ,  G06F13/28 ,  G06F12/122

CPC分类号： G06F12/084 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/601 ,  G06F2212/6042

摘要： A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.