公开(公告)号：US10437320B2

公开(公告)日：2019-10-08

申请号：US15256050

申请日：2016-09-02

申请人： Intel Corporation

发明人： Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F1/3293 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/20 ,  G06F1/3206 ,  G06F9/50 ,  G06F13/24 ,  G06F9/38 ,  G06F9/46 ,  G06F1/3228 ,  G06F1/20 ,  G06F1/3287 ,  G06F12/0875

摘要： Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

公开(公告)号：US09760162B2

公开(公告)日：2017-09-12

申请号：US14033008

申请日：2013-09-20

申请人： Intel Corporation

发明人： Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

IPC分类号： G06F9/00 ,  G06F1/32 ,  G06T1/20 ,  G06F9/50 ,  G06F13/24 ,  G06F9/38 ,  G06F9/46 ,  G06F1/20 ,  G06F12/0875

CPC分类号： G06F1/3293 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3869 ,  G06F9/461 ,  G06F9/5088 ,  G06F9/5094 ,  G06F12/0875 ,  G06F13/24 ,  G06F2209/5017 ,  G06F2212/452 ,  G06T1/20 ,  Y02B70/10 ,  Y02B70/1425 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

公开(公告)号：US20190188136A1

公开(公告)日：2019-06-20

申请号：US16281941

申请日：2019-02-21

申请人： Intel Corporation

发明人： Pinkesh Shah ,  Herbert Hum ,  Lingdan Zeng

IPC分类号： G06F12/084 ,  G06F13/28 ,  G06F12/122

CPC分类号： G06F12/084 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/601 ,  G06F2212/6042

摘要： A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.

公开(公告)号：US09939882B2

公开(公告)日：2018-04-10

申请号：US13954977

申请日：2013-07-31

申请人： Intel Corporation

发明人： Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

IPC分类号： G06F9/00 ,  G06F15/177 ,  G06F1/32 ,  G06T1/20 ,  G06F9/50 ,  G06F13/24 ,  G06F9/38 ,  G06F9/46 ,  G06F1/20 ,  G06F12/0875

CPC分类号： G06F1/3293 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3869 ,  G06F9/461 ,  G06F9/5088 ,  G06F9/5094 ,  G06F12/0875 ,  G06F13/24 ,  G06F2209/5017 ,  G06F2212/452 ,  G06T1/20 ,  Y02B70/10 ,  Y02B70/1425 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system.

公开(公告)号：US10409360B2

公开(公告)日：2019-09-10

申请号：US15256101

申请日：2016-09-02

申请人： Intel Corporation

发明人： Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

IPC分类号： G06F1/24 ,  G06F1/3293 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/20 ,  G06F1/3206 ,  G06F9/50 ,  G06F13/24 ,  G06F9/38 ,  G06F9/46 ,  G06F1/3228 ,  G06F1/20 ,  G06F1/3287 ,  G06F12/0875

摘要： Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

公开(公告)号：US09880935B2

公开(公告)日：2018-01-30

申请号：US14222792

申请日：2014-03-24

申请人： Intel Corporation

发明人： Pinkesh Shah ,  Herbert Hum ,  Lingdan Zeng

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F13/28 ,  G06F12/084 ,  G06F12/122

CPC分类号： G06F12/084 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/601 ,  G06F2212/6042

摘要： A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.

公开(公告)号：US09870046B2

公开(公告)日：2018-01-16

申请号：US13954979

申请日：2013-07-31

申请人： Intel Corporation

发明人： Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

IPC分类号： G06F1/24 ,  G06F9/00 ,  G06F1/32 ,  G06T1/20 ,  G06F9/50 ,  G06F13/24 ,  G06F9/38 ,  G06F9/46 ,  G06F1/20 ,  G06F12/0875

CPC分类号： G06F1/3293 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3869 ,  G06F9/461 ,  G06F9/5088 ,  G06F9/5094 ,  G06F12/0875 ,  G06F13/24 ,  G06F2209/5017 ,  G06F2212/452 ,  G06T1/20 ,  Y02B70/10 ,  Y02B70/1425 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system

公开(公告)号：US10248568B2

公开(公告)日：2019-04-02

申请号：US15879030

申请日：2018-01-24

申请人： Intel Corporation

发明人： Pinkesh Shah ,  Herbert Hum ,  Lingdan Zeng

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F13/28 ,  G06F12/084 ,  G06F12/122

摘要： A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.

公开(公告)号：US20180165193A1

公开(公告)日：2018-06-14

申请号：US15879030

申请日：2018-01-24

申请人： Intel Corporation

发明人： Pinkesh Shah ,  Herbert Hum ,  Lingdan Zeng

IPC分类号： G06F12/084 ,  G06F13/28 ,  G06F12/122

CPC分类号： G06F12/084 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/601 ,  G06F2212/6042

摘要： A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.

公开(公告)号：US09829965B2

公开(公告)日：2017-11-28

申请号：US14498014

申请日：2014-09-26

申请人： INTEL CORPORATION

发明人： Herbert Hum ,  Eric Sprangle ,  Douglas Carmean ,  Rajesh Kumar

IPC分类号： G06F1/24 ,  G06F9/00 ,  G06F1/32 ,  G06T1/20 ,  G06F9/50 ,  G06F13/24 ,  G06F9/38 ,  G06F9/46 ,  G06F1/20 ,  G06F12/0875

CPC分类号： G06F1/3293 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3869 ,  G06F9/461 ,  G06F9/5088 ,  G06F9/5094 ,  G06F12/0875 ,  G06F13/24 ,  G06F2209/5017 ,  G06F2212/452 ,  G06T1/20 ,  Y02B70/10 ,  Y02B70/1425 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： Techniques are disclosed to control power and processing among a plurality of asymmetric cores. In one embodiment, a multi-core processor includes first and second processing cores, each including an arithmetic logic unit and an instruction decoder, wherein the first processing core is capable of operating at a higher processing throughput than the second processing core, wherein the first and second processing cores have different instruction sets, wherein, in response to an occurrence of an event, a task processed on the first processing core is to be translated and transferred to the second processing core after saving a core state of the first processing core and providing the core state to the second processing core, wherein instructions to run on the second processing core are translated to the instruction set of the second processing core by a software binary translation shell, and wherein the first and second processing cores are to concurrently execute instructions according to their own instruction sets.