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    I3C PENDING READ WITH RETRANSMISSION
    2.
    发明申请
    I3C PENDING READ WITH RETRANSMISSION 有权

    公开(公告)号：US20210109887A1

    公开(公告)日：2021-04-15

    申请号：US17128384

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： JANUSZ JURSKI ,  ENRICO DAVID CARRIERI ,  AMIT KUMAR SRIVASTAVA ,  MATTHEW A. SCHNOOR ,  MYRON LOEWEN

    IPC: G06F13/42 ,  G06F13/362 ,  G06F13/24 ,  G06F9/54

    Abstract: Embodiments of the present disclosure may relate to apparatus, process, or techniques in a I3C protocol environment that include identifying a pending read notification message by a slave device to be sent to a master device to indicate that the data is available to be read by the master device from a buffer associated with the slave device. The pending read notification may be subsequently transmitted to the master device. Subsequently, until the data in the buffer has been read by the master device, the slave device may wait an identified amount of time that is less than a value of a timeout of the master device, and retransmit the pending read notification message to the master device. Other embodiments may be described and/or claimed.

    FUNCTIONAL SAFETY CLOCKING FRAMEWORK FOR REAL TIME SYSTEMS
    3.
    发明申请
    FUNCTIONAL SAFETY CLOCKING FRAMEWORK FOR REAL TIME SYSTEMS 审中-公开

    公开(公告)号：US20190052277A1

    公开(公告)日：2019-02-14

    申请号：US16017865

    申请日：2018-06-25

    Applicant: Intel Corporation

    Inventor： JAGANNADHA RAO RAPETA ,  ASAD AZAM ,  AMIT KUMAR SRIVASTAVA ,  MIKAL HUNSAKER

    IPC: H03L7/08 ,  G05B9/03 ,  H03L7/081

    Abstract: Methods and apparatus relating to functional safety clocking framework for real time systems are described. In an embodiment, clock monitoring logic circuitry monitors a plurality of clock signals. Safety island logic circuitry receives an error status signal from the clock monitoring logic circuitry based at least in part on a determination of whether an error exists for at least one of the plurality of clock signals. Safety logic circuitry to receive an interrupt signal from the safety island logic circuitry in response to a determination that the error status signal indicates existence of an error for at least one of the plurality of clock signals. Other embodiments are also disclosed and claimed.

    ELECTRICAL FAST TRANSIENT TOLERANT INPUT/OUTPUT (I/O) COMMUNICATION SYSTEM
    5.
    发明申请
    ELECTRICAL FAST TRANSIENT TOLERANT INPUT/OUTPUT (I/O) COMMUNICATION SYSTEM 有权

    公开(公告)号：US20170123470A1

    公开(公告)日：2017-05-04

    申请号：US14925713

    申请日：2015-10-28

    Applicant: Intel Corporation

    Inventor： AMIT KUMAR SRIVASTAVA

    IPC: G06F1/26 ,  G06F13/42

    CPC classification number: G06F1/266 ,  G06F13/4282

    Abstract: Apparatuses, systems and methods associated with electrical fast transient tolerant input/output (I/O) communication (e.g., universal serial bus (USB)) design are disclosed herein. In embodiments, an apparatus may include common mode extraction circuitry to extract a common mode voltage from a USB input signal for a USB device, compare the common mode voltage with a reference voltage range and determine, based on the comparison, that the common mode voltage is outside of the reference voltage range. In the embodiments, the apparatus may further include processing circuitry to adjust the common mode voltage to within the reference voltage range. Other embodiments may be described and/or claimed.

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