公开(公告)号：US20210192674A1

公开(公告)日：2021-06-24

申请号：US17096590

申请日：2020-11-12

Applicant: Intel Corporation

Inventor： Konstantin Levit-Gurevich ,  Michael Berezalsky ,  Noam Itzhaki ,  Arik Narkis ,  Orr Goldman

IPC: G06T1/20 ,  G06F9/50 ,  G06T1/60 ,  G06F11/34

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve operation of a graphics processing unit (GPU). An example apparatus includes an instruction generator to insert profiling instructions into a GPU kernel to generate an instrumented GPU kernel, the instrumented GPU kernel is to be executed by a GPU, a trace analyzer to generate an occupancy map associated with the GPU executing the instrumented GPU kernel, a parameter calculator to determine one or more operating parameters of the GPU based on the occupancy map, and a processor optimizer to invoke a GPU driver to adjust a workload of the GPU based on the one or more operating parameters.

公开(公告)号：US20220012844A1

公开(公告)日：2022-01-13

申请号：US17484942

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Konstantin Levit-Gurevich ,  Michael Berezalsky ,  Noam Itzhaki ,  Arik Narkis ,  Orr Goldman

IPC: G06T1/20 ,  G06F9/455 ,  G06T1/60 ,  G06F9/38 ,  G06F9/50

Abstract: Embodiments are disclosed for emulation of graphics processing unit instructions. An example method executing an instrumented kernel using a logic circuit, the instrumented kernel including an emulation sequence; saving, in response to determination that the emulation sequence is to be executed, source data to a shared memory; setting an emulation request flag to indicate to processor circuitry separate from the logic circuit that offloaded execution of the emulation sequence is to be executed; monitoring the emulation request flag to determine whether the offloaded execution of the emulation sequence is complete; and accessing resulting data from the shared memory.

公开(公告)号：US10467118B2

公开(公告)日：2019-11-05

申请号：US15718435

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Konstantin Levit-Gurevich ,  Michael Berezalsky ,  Noam Itzhaki ,  Arik Narkis

IPC: G06F9/44 ,  G06F11/34 ,  G06F11/30 ,  G06F11/36

Abstract: Techniques and apparatus for performance analysis of a program are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of comprised in hardware coupled to the at least one memory, to access a program for performance analysis, the program comprising at least one producer instruction and at least one consumer instruction for the at least one producer instruction, and generate an analysis program based on the program, the analysis program comprising a stall time instruction set to determine a stall time of the at least one producer instruction, the stall time instruction set comprising a first time stamp instruction immediately preceding a consumer instruction, a second time stamp instruction immediately following the consumer instruction, and a stall time instruction to determine the stall time as the difference between the second time stamp and the first time stamp. Other embodiments are described and claimed.

公开(公告)号：US11694299B2

公开(公告)日：2023-07-04

申请号：US17484942

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Konstantin Levit-Gurevich ,  Michael Berezalsky ,  Noam Itzhaki ,  Arik Narkis ,  Orr Goldman

IPC: G06T1/20 ,  G06F9/455 ,  G06T1/60 ,  G06F9/38 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06F9/3877 ,  G06F9/455 ,  G06F9/5055 ,  G06T1/60

Abstract: Embodiments are disclosed for emulation of graphics processing unit instructions. An example method executing an instrumented kernel using a logic circuit, the instrumented kernel including an emulation sequence; saving, in response to determination that the emulation sequence is to be executed, source data to a shared memory; setting an emulation request flag to indicate to processor circuitry separate from the logic circuit that offloaded execution of the emulation sequence is to be executed; monitoring the emulation request flag to determine whether the offloaded execution of the emulation sequence is complete; and accessing resulting data from the shared memory.

公开(公告)号：US11132761B2

公开(公告)日：2021-09-28

申请号：US16783878

申请日：2020-02-06

Applicant: Intel Corporation

Inventor： Konstantin Levit-Gurevich ,  Michael Berezalsky ,  Noam Itzhaki ,  Arik Narkis ,  Orr Goldman

IPC: G06T1/20 ,  G06F9/455 ,  G06T1/60 ,  G06F9/38 ,  G06F9/50

Abstract: Embodiments are disclosed for emulation of graphics processing unit instructions. An example apparatus includes a kernel accessor to access an instruction of an original GPU kernel, the original GPU kernel intended to be executed at a first GPU. An instruction support determiner is to determine whether execution of the instruction is supported by a second GPU different from the first GPU. An instruction modifier is to, in response to determining that the execution of the instruction is not supported by the second GPU, create an instrumented GPU kernel based on the original GPU kernel. The instrumented GPU kernel includes an emulation sequence. The emulation sequence is to, when executed by the second GPU, cause the second GPU to emulate execution of the instruction by the first GPU.

公开(公告)号：US10922779B2

公开(公告)日：2021-02-16

申请号：US16235304

申请日：2018-12-28

Applicant: INTEL CORPORATION

Inventor： Orr Goldman ,  Konstantin Levit-Gurevich ,  Michael Berezalsky ,  Noam Itzhaki ,  Arik Narkis

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: Techniques and apparatus for profiling graphics processing unit (GPU) processes using binary instrumentation are described. In one embodiment, for example, an apparatus may include at least one memory comprising instructions and a processor coupled to the at least one memory. The processor may execute the instructions to determine a plurality of profiling modes for profiling an operating process of a graphics processing unit (GPU) application, access original binary code for the GPU application, and generate a multi-mode instrumented binary code comprising a plurality of instrumentation modes, each of the plurality of instrumentation modes corresponding to at least one of the plurality of profiling modes. Other embodiments are described.

公开(公告)号：US20230281104A1

公开(公告)日：2023-09-07

申请号：US18316866

申请日：2023-05-12

Applicant: Intel Corporation

Inventor： Konstantin Levit-Gurevich ,  Aleksey Alekseev ,  Michael Berezalsky ,  Sion Berkowits ,  Julia Fedorova ,  Anton V. Gorshkov ,  Sunpyo Hong ,  Noam Itzhaki ,  Arik Narkis

IPC: G06F11/36 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F11/3612 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3466 ,  G06F8/41

Abstract: Disclosed examples include generating instrumented code by inserting profiling instructions at insertion points in code; outputting the instrumented code for execution by second programmable circuitry; and accessing profiling data generated by the second programmable circuitry based on the instrumented code.

公开(公告)号：US11650902B2

公开(公告)日：2023-05-16

申请号：US15806917

申请日：2017-11-08

Applicant: Intel Corporation

Inventor： Konstantin Levit-Gurevich ,  Aleksey Alekseev ,  Michael Berezalsky ,  Sion Berkowits ,  Julia Fedorova ,  Anton V. Gorshkov ,  Sunpyo Hong ,  Noam Itzhaki ,  Arik Narkis

IPC: G06F11/36 ,  G06F11/30 ,  G06F11/34 ,  G06F8/41

CPC classification number: G06F11/3612 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3466 ,  G06F8/41 ,  G06F2201/865

Abstract: Disclosed examples to perform instruction-level graphics processing unit (GPU) profiling based on binary instrumentation include: accessing, via a GPU driver executed by a processor, binary code generated by a GPU compiler based on application programming interface (API)-based code provided by an application; accessing, via the GPU driver executed by the processor, instrumented binary code, the instrumented binary code generated by a binary instrumentation module that inserts profiling instructions in the binary code based on an instrumentation schema provided by a profiling application; and providing, via the GPU driver executed by the processor, the instrumented binary code from the GPU driver to a GPU, the instrumented binary code structured to cause the GPU to collect and store profiling data in a memory based on the profiling instructions while executing the instrumented binary code.

公开(公告)号：US10559057B2

公开(公告)日：2020-02-11

申请号：US16144290

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Konstantin Levit-Gurevich ,  Michael Berezalsky ,  Noam Itzhaki ,  Arik Narkis ,  Orr Goldman

IPC: G06T1/20 ,  G06F9/455 ,  G06T1/60 ,  G06F9/38 ,  G06F9/50

Abstract: Embodiments are disclosed for emulation of graphics processing unit instructions. An example apparatus includes a kernel accessor to access an instruction of an original GPU kernel, the original GPU kernel intended to be executed at a first GPU. An instruction support determiner is to determine whether execution of the instruction is supported by a second GPU different from the first GPU. An instruction modifier is to, in response to determining that the execution of the instruction is not supported by the second GPU, create an instrumented GPU kernel based on the original GPU kernel. The instrumented GPU kernel includes an emulation sequence. The emulation sequence is to, when executed by the second GPU, cause the second GPU to emulate execution of the instruction by the first GPU.

公开(公告)号：US10459705B2

公开(公告)日：2019-10-29

申请号：US15856743

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Anton V. Gorshkov ,  Michael Berezalsky ,  Konstantin Levit-Guervich ,  Julia Fedorova ,  Noam Itzhaki ,  Arik Narkis ,  Sion Berkowits

IPC: G06F8/41 ,  G06F11/34

Abstract: Systems, apparatuses and methods may provide for technology that receives compiled code and identifies a plurality of blocks in the compiled code. Instrumented code may be generated from the compiled code by modifying the blocks to include probes to measure latencies of the blocks during execution of the instrumented code on a graphics processing unit.