公开(公告)号：US20190042130A1

公开(公告)日：2019-02-07

申请号：US15845596

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： NAVEEN VITTAL PRABHU ,  ALIASGAR S. MADRASWALA ,  DONIA SEBASTIAN ,  SHANKAR NATARAJAN

IPC: G06F3/06

Abstract: A system for reconfiguring flash memory from a default access operation mode (e.g., MLC, TLC, or QLC mode) to a non-default access operation mode (e.g., SLC mode) using opcode prefixes is provided. Opcode prefix logic enables the flash memory die to enter a non-default (e.g., faster) access operation mode. The non-default access operation mode is entered by providing a prefix instruction or opcode prefix to the memory controller and/or to the flash memory die prior to memory operation commands (“opcode”) for program, read, and/or erase. The flash memory die is configured to automatically exit the non-default access operation mode after a single operation, or the flash memory die is configured to exit the non-default access operation mode upon receipt of another opcode prefix.

公开(公告)号：US20190043564A1

公开(公告)日：2019-02-07

申请号：US15845500

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： ALIASGAR S. MADRASWALA ,  BHARAT M. PATHAK ,  BINH N. NGO ,  NAVEEN VITTAL PRABHU ,  KARTHIKEYAN RAMAMURTHI ,  PRANAV KALAVADE

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G11C8/08 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C2211/5631

Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.