公开(公告)号：US20250006808A1

公开(公告)日：2025-01-02

申请号：US18215743

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mohammad HASAN ,  Charles H. WALLACE

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: Integrated circuit structures having internal spacer liners, and methods of fabricating integrated circuit structures having internal spacer liners, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent ones of the stack of horizontal nanowires and laterally adjacent to the gate structure. An internal spacer liner is intervening between the internal gate spacer and the vertically adjacent ones of the stack of horizontal nanowires, and the internal spacer liner is intervening between the internal gate spacer and the gate structure.

公开(公告)号：US20230197854A1

公开(公告)日：2023-06-22

申请号：US17553161

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tahir GHANI ,  Charles H. WALLACE ,  Mohit K. HARAN ,  Mohammad HASAN ,  Aryan NAVABI-SHIRAZI ,  Allen B. GARDINER

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/78618 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/785 ,  H01L29/0847 ,  H01L29/42392

Abstract: Integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, and methods of fabricating integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the plurality of horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A confined epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure, the dielectric anchor having an uppermost surface below an uppermost surface of the confined epitaxial source or drain structure.

公开(公告)号：US20230317786A1

公开(公告)日：2023-10-05

申请号：US17700215

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Cory WEBER ,  Varun MISHRA ,  Tahir GHANI ,  Pratik PATEL ,  Wonil CHUNG ,  Mohammad HASAN

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/0673 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439

Abstract: Gate-all-around integrated circuit structures having necked features, and methods of fabricating gate-all-around integrated circuit structures having necked features, are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires. Each nanowire of the vertical stack of horizontal nanowires has a channel portion with a first vertical thickness and has end portions with a second vertical thickness greater than the first vertical thickness. A gate stack is surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires.

公开(公告)号：US20230197713A1

公开(公告)日：2023-06-22

申请号：US17554442

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Guillaume BOUCHE ,  Andy Chih-Hung WEI ,  Anand S. MURTHY ,  Aryan NAVABI-SHIRAZI ,  Mohammad HASAN

IPC: H01L27/088 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L27/088 ,  H01L21/823814 ,  H01L21/823412 ,  H01L27/092 ,  H01L21/823481 ,  H01L21/823418

Abstract: Gate-all-around integrated circuit structures having raised wall structures for epitaxial source or drain region confinement are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and the second epitaxial source or drain structures. The intervening dielectric structure has a top surface above a top surface of the first and second vertical arrangements of nanowires. The intervening dielectric structure has a width at the top surface of the intervening dielectric structure less than a width below the top surface of the intervening dielectric structure.

公开(公告)号：US20230093657A1

公开(公告)日：2023-03-23

申请号：US17482228

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Mohit K. HARAN ,  Mohammad HASAN ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: Integrated circuit structures having a dielectric gate wall and a dielectric gate plug, and methods of fabricating integrated circuit structures having a dielectric gate wall and a dielectric gate plug, are described. For example, an integrated circuit structure includes a sub-fin having a portion protruding above a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is over the protruding portion of the sub-fin, over the STI structure, and surrounding the horizontally stacked nanowires. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate wall is laterally spaced apart from the sub-fin and the plurality of horizontally stacked nanowires, the dielectric gate wall on the STI structure. A dielectric gate plug is on the dielectric gate wall.

公开(公告)号：US20250006547A1

公开(公告)日：2025-01-02

申请号：US18215741

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Mohammad HASAN ,  Angel AQUINO GONZALEZ ,  Tahir GHANI ,  Conor P. PULS ,  Mitali CHINA

IPC: H01L21/762 ,  H01L29/775 ,  H01L29/78

Abstract: Integrated circuit structures having removed sub-fins, and methods of fabricating integrated circuit structures having removed sub-fins, are described. For example, an integrated circuit structure includes a channel structure, and a sub-fin isolation structure in a trench beneath the channel structure, wherein there is no residual silicon portion in the trench.

公开(公告)号：US20240347539A1

公开(公告)日：2024-10-17

申请号：US18752147

申请日：2024-06-24

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Mohit K. HARAN ,  Mohammad HASAN ,  Biswajeet GUHA ,  Alison V. DAVIS ,  Leonard P. GULER

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the STI structure. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.

公开(公告)号：US20230317789A1

公开(公告)日：2023-10-05

申请号：US17710841

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Anand S. MURTHY ,  Cory BOMBERGER ,  Subrina RAFIQUE ,  Chi-Hing CHOI ,  Mohammad HASAN

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/775 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/0673 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/0847 ,  H01L29/41783

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with selective silicide contacts thereon are described. In an example, an integrated circuit structure includes a plurality of stacks of nanowires. A plurality of epitaxial source or drain structures is around ends of corresponding ones of the stacks of nanowires. A silicide layer is on an entirety of a top surface of the plurality of epitaxial source or drain structures. A conductive trench contact is on the silicide layer. A dielectric layer is vertically intervening between a portion of the conductive trench contact and the silicide layer.

公开(公告)号：US20230178622A1

公开(公告)日：2023-06-08

申请号：US17544724

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Clifford ONG ,  Mohammad HASAN ,  Tahir GHANI ,  Charles H. WALLACE

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/66742 ,  H01L29/401

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a directed bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. A gate stack is over and around the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires, the second end opposite the first end, wherein at least one of the first or second epitaxial source or drain structures is coupled to fewer than all nanowires of the vertical arrangement of nanowires.

公开(公告)号：US20220415890A1

公开(公告)日：2022-12-29

申请号：US17359320

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Mohammad HASAN ,  Biswajeet GUHA ,  Oleg GOLONZKA ,  Leonard P. GULER ,  Leah SHOER ,  Daniel G. OUELLETTE ,  Pedro FRANCO NAVARRO ,  Tahir GHANI

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78

Abstract: Integrated circuit structures having metal gates with tapered plugs, and methods of fabricating integrated circuit structures having metal gates with tapered plugs, are described. For example, includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin. The dielectric gate plug is on the STI structure, and the dielectric gate plug has sides tapered outwardly from a top of the dielectric gate plug to a bottom of the dielectric gate plug.