公开(公告)号：US20190079681A1

公开(公告)日：2019-03-14

申请号：US15699930

申请日：2017-09-08

Applicant: Intel Corporation

Inventor： SANJEEV N. TRIKA ,  PENG LI ,  JAWAD B. KHAN

IPC: G06F3/06 ,  H03M13/29 ,  G06F11/10 ,  G11C29/52 ,  G06F12/1009

CPC classification number: G06F3/0616 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0665 ,  G06F3/0673 ,  G06F3/0679 ,  G06F11/1004 ,  G06F11/1048 ,  G06F11/1068 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1036 ,  G11C29/52 ,  H03M13/2906

Abstract: One embodiment provides a memory controller. The memory controller includes logical block address (LBA) section defining logic to define a plurality of LBA sections for a memory device circuitry, each section including a range of LB As, and each section including a unique indirection-unit (IU) granularity; wherein the IU granularity defines a physical region size of the memory device. The LBA section defining logic also to generate a plurality of logical-to-physical (L2P) tables to map a plurality of LBAs to physical locations of the memory device, each L2P table corresponding to an LBA section. The memory controller also includes LBA section notification logic to notify a file system of the plurality of LBA sections to enable the file system to issue a read and/or write command having an LBA based on an IU granularity associated with an LBA section.

公开(公告)号：US20190034088A1

公开(公告)日：2019-01-31

申请号：US15836704

申请日：2017-12-08

Applicant: Intel Corporation

Inventor： PENG LI ,  SANJEEV N. TRIKA

IPC: G06F3/06 ,  G06F12/10 ,  G06F13/28

Abstract: Embodiments of the present disclosure may relate to a data storage controller that may include a host interface to receive a request from a host to perform a data copy operation on a non-volatile data storage component of a data storage device, where the request identifies one or more source ranges of the non-volatile data storage component from which data is to be copied, a destination range of the non-volatile data storage component to which the data is to be copied, and a transfer length in bytes for each of the one or more source ranges, and a processor coupled with the host interface to process the request from the host to perform the data copy operation to copy the data from the one or more source ranges to the destination range based at least in part on the transfer length in bytes. Other embodiments may be described and/or claimed.

公开(公告)号：US20190004726A1

公开(公告)日：2019-01-03

申请号：US15639450

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： PENG LI ,  JAWAD B. KHAN ,  SANJEEV N. TRIKA ,  VINODH GOPAL

IPC: G06F3/06

Abstract: One embodiment provides an apparatus. The apparatus include a device storage logic. The device storage logic is to determine a key-based pointer based, at least in part, on a key included in an input key-value (KV) pair received from a host device and to determine whether a unique input KV data block included in the input KV pair is duplicated in a nonvolatile memory circuitry of a storage device. The device storage logic is further to set a descriptor pointer associated with the unique input KV data block to point to a physical nonvolatile memory (NVM) address associated with an existing unique data block and increment a first reference count associated with the existing unique data block, if the unique input KV data block is a duplicate of the existing unique data block, or store the input KV data block to a physical NVM location associated with a selected physical NVM address, set the descriptor pointer to point to the selected physical NVM address and set a second reference count associated with the selected physical NVM address to one, if the unique input KV data block is not duplicated in the NVM circuitry.