公开(公告)号：US20180204932A1

公开(公告)日：2018-07-19

申请号：US15570965

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Partick MORROW ,  Ranjith KUMAR ,  Cory E. WEBER ,  Seiyon KIM ,  Stephen M. CEA ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L27/108

CPC classification number: H01L29/66795 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/10826 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/78 ,  H01L29/785

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.