公开(公告)号：US20250113595A1

公开(公告)日：2025-04-03

申请号：US18374607

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Tao CHU ,  Minwoo JANG ,  Yanbin LUO ,  Paul PACKAN ,  Guowei XU ,  Chiao-Ti HUANG ,  Robin CHAO ,  Feng ZHANG ,  Ting-Hsiang HUNG ,  Chia-Ching LIN ,  Yang ZHANG ,  Chung-Hsun LIN ,  Anand S. MURTHY

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Multiple voltage threshold integrated circuit structures with local layout effect tuning, and methods of fabricating multiple voltage threshold integrated circuit structures with local layout effect tuning, are described. For example, an integrated circuit structure includes a first fin structure or vertical arrangement of horizontal nanowires. A second fin structure or vertical arrangement of horizontal nanowires is laterally spaced apart from the first fin structure or vertical arrangement of horizontal nanowires. An N-type gate structure is over the first fin structure or vertical arrangement of horizontal nanowires. A P-type gate structure is over the second fin structure or vertical arrangement of horizontal nanowires, the P-type gate structure in contact with the N-type gate structure with a PN boundary between the P-type gate structure and the N-type gate structure. The PN boundary is offset from a central location between the first fin structure or vertical arrangement of horizontal nanowires and the second fin structure or vertical arrangement of horizontal nanowires.

公开(公告)号：US20250107175A1

公开(公告)日：2025-03-27

申请号：US18372506

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Tao CHU ,  Minwoo JANG ,  Yanbin LUO ,  Paul PACKAN ,  Guowei XU ,  Chiao-Ti HUANG ,  Robin CHAO ,  Feng ZHANG ,  Ting-Hsiang HUNG ,  Chia-Ching LIN ,  Yang ZHANG ,  Chung-Hsun LIN ,  Anand S. MURTHY

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated circuit structures having reduced local layout effects, and methods of fabricating integrated circuit structures having reduced local layout effects, are described. For example, an integrated circuit structure includes an NMOS region including a first plurality of fin structures or vertical stacks of horizontal nanowires, and first alternating gate lines and trench contact structures over the first plurality of fin structures or vertical stacks of horizontal nanowires. The integrated circuit structure also includes a PMOS region including a second plurality of fin structures or vertical stacks of horizontal nanowires, and second alternating gate and trench contact structures over the second plurality of fin structures or vertical stacks of horizontal nanowires. A gate line is shared between the NMOS region and the PMOS region, and a trench contact structure is shared between the NMOS region and the PMOS region. Ends of the gate line shared between the NMOS region and the PMOS region are offset from ends of the trench contact structure shared between the NMOS region and the PMOS region.

公开(公告)号：US20250112120A1

公开(公告)日：2025-04-03

申请号：US18375084

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Tao CHU ,  Minwoo JANG ,  Yanbin LUO ,  Paul PACKAN ,  Conor P. PULS ,  Guowei XU ,  Chiao-Ti HUANG ,  Robin CHAO ,  Feng ZHANG ,  Ting-Hsiang HUNG ,  Chia-Ching LIN ,  Yang ZHANG ,  Chung-Hsun LIN ,  Anand S. MURTHY

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having deep via bar width tuning are described. For example, an integrated circuit structure includes a plurality of gate lines extending over first and second semiconductor nanowire stack channel structures or fin structures. A plurality of trench contacts is intervening with the plurality of gate lines. A conductive structure is between the first and second semiconductor nanowire stack channel structures or fin structures, the conductive structure having a first width in a first region and a second width in a second region between the first and second semiconductor nanowire stack channel structures or fin structures, the second width different than the first width.

公开(公告)号：US20170186855A1

公开(公告)日：2017-06-29

申请号：US15461427

申请日：2017-03-16

Applicant: Intel Corporation

Inventor： Anand S. Murthy ,  Robert S. CHAU ,  Patrick MORROW ,  Chia-Hong JAN ,  Paul PACKAN

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.