公开(公告)号：US20210042147A1

公开(公告)日：2021-02-11

申请号：US17080970

申请日：2020-10-27

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Robert De Gruijl ,  Sridhar Lakshmanamurthy ,  Ramadass Nagarajan ,  Peter J. Elardo

IPC: G06F9/46 ,  G06F15/76 ,  G06F15/78 ,  G06F13/42

Abstract: In one embodiment, a system on chip includes a first endpoint to issue a non-posted memory write transaction to a memory and a Peripheral Component Interconnect (PCI)-based fabric including control logic to direct the non-posted memory write transaction to the memory, receive a completion for the non-posted memory write transaction from the memory and route the completion to the first endpoint. Other embodiments are described and claimed.

公开(公告)号：US20160188529A1

公开(公告)日：2016-06-30

申请号：US14583142

申请日：2014-12-25

Applicant: Intel Corporation

Inventor： Ramadass Nagarajan ,  Michael T. Klinglesmith ,  Marc Torrant ,  James A. Coleman ,  Peter J. Elardo ,  Eric A. Geisler

IPC: G06F15/78 ,  G06F13/16 ,  G06F13/18 ,  G06F12/08

CPC classification number: G06F15/7814 ,  G06F12/0811 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/18 ,  G06F15/781 ,  G06F2212/314 ,  Y02D10/13 ,  Y02D10/14

Abstract: In an example, a control system may include a system-on-a-chip (SoC), including one processor for real-time operation to manage devices in the control system, and another processor configured to execute auxiliary functions such as a user interface for the control system. The first core and second core may share memory such as dynamic random access memory (DRAM), and may also share an uncore fabric configured to communicatively couple the processors to one or more peripheral devices. The first core may require a guaranteed quality of service (QoS) to memory and/or peripherals. The uncore fabric may be divided into a first “real-time” virtual channel designated for traffic from the first processor, and a second “auxiliary” virtual channel designated for traffic from the second processor. The uncore fabric may apply a suitable selection or weighting algorithm to the virtual channels to guarantee the QoS.

Abstract translation: 在一个示例中，控制系统可以包括片上系统（SoC），其包括用于实时操作的一个处理器来管理控制系统中的设备，以及另一处理器，其被配置为执行辅助功能，例如用户接口 用于控制系统。 第一核心和第二核心可以共享诸如动态随机存取存储器（DRAM）的存储器，并且还可以共享被配置为将处理器通信地耦合到一个或多个外围设备的非空心结构。 第一个核心可能需要对存储器和/或外设的有保证的服务质量（QoS）。 非空心结构可以被划分为从第一处理器指定用于业务的第一“实时”虚拟通道和被指定用于来自第二处理器的业务的第二“辅助”虚拟通道。 不织布可以对虚拟信道应用合适的选择或加权算法来保证QoS。

公开(公告)号：US20180181432A1

公开(公告)日：2018-06-28

申请号：US15391984

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Robert De Gruijl ,  Sridhar Lakshmanamurthy ,  Ramadass Nagarajan ,  Peter J. Elardo

IPC: G06F9/46 ,  G06F13/42 ,  G06F15/78

CPC classification number: G06F9/467 ,  G06F13/4282 ,  G06F15/76 ,  G06F15/781 ,  G06F2213/0026

Abstract: In one embodiment, a system on chip includes a first endpoint to issue a non-posted memory write transaction to a memory and a Peripheral Component Interconnect (PCI)-based fabric including control logic to direct the non-posted memory write transaction to the memory, receive a completion for the non-posted memory write transaction from the memory and route the completion to the first endpoint. Other embodiments are described and claimed.

公开(公告)号：US11372674B2

公开(公告)日：2022-06-28

申请号：US17080970

申请日：2020-10-27

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Robert De Gruijl ,  Sridhar Lakshmanamurthy ,  Ramadass Nagarajan ,  Peter J. Elardo

IPC: G06F9/46 ,  G06F13/42 ,  G06F15/78 ,  G06F15/76

Abstract: In one embodiment, a system on chip includes a first endpoint to issue a non-posted memory write transaction to a memory and a Peripheral Component Interconnect (PCI)-based fabric including control logic to direct the non-posted memory write transaction to the memory, receive a completion for the non-posted memory write transaction from the memory and route the completion to the first endpoint. Other embodiments are described and claimed.