公开(公告)号：US20180358292A1

公开(公告)日：2018-12-13

申请号：US15974493

申请日：2018-05-08

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Wen Wei LUM ,  Mooi Ling CHANG ,  Ping Ping OOI

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5223 ,  H01L23/315 ,  H01L24/09 ,  H01L2224/0233

Abstract: Over-molded IC package assemblies including an in-mold capacitor. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more capacitors are fabricated within the molding compound. The capacitors may include two or more metal plates separated by an intervening dielectric material, all of which are embedded within a trench in the molding compound. Individual ones of the capacitor plates may physically contact a conductive land of the package redistribution layer or package substrate, for example to tie the plates to a ground plane and power plane, or two supply rails, in a decoupling capacitor application.

公开(公告)号：US20180294252A1

公开(公告)日：2018-10-11

申请号：US15766150

申请日：2015-11-05

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Ping Ping OOI ,  Kooi Chi OOI ,  Shanggar PERIAMAN

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1816 ,  H01L2924/18162 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed toward a stacked package assembly for embedded dies and associated techniques and configurations. In one embodiment, stacked package assembly may comprise a first die package and a second die package stacked one upon the other with plural interconnections between them; and a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.

公开(公告)号：US20180366407A1

公开(公告)日：2018-12-20

申请号：US15982912

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Ping Ping OOI ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Mooi Ling CHANG ,  Wen Wei LUM

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/50 ,  H01L23/367

Abstract: Over-molded IC package assemblies including an embedded voltage reference plane and/or heat spreader. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more conductive layers are embedded within the molding compound. The conductive layers may include an interior portion located over the IC chip and a peripheral portion located over the redistribution layers or package substrate. The interior portion may comprise one or more heat conductive features, which may physically contact a surface of the IC chip. In some further embodiments, the peripheral portion comprises one or more electrically conductive features, which may physically contact a surface of the package redistribution layers or package substrate to convey a reference voltage. One or more conductive traces may connect the conductive features in the interior with conductive features in the periphery.