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    Adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications
    1.
    发明授权
    Adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications 有权
    自适应控制回路保护，用于在高速串行I / O应用中从低功耗状态进行快速和强劲的恢复

    公开(公告)号：US09436244B2

    公开(公告)日：2016-09-06

    申请号：US13831892

    申请日：2013-03-15

    Applicant: Intel Corporation

    Inventor： Yun He ,  Narender R. Nagulapally ,  Sanjib Sarkar ,  Ivan Herrera Mejia ,  Ruchira K. Liyanage

    IPC: G06F1/32 ,  G06F1/26 ,  G06F11/07 ,  G06F1/00

    CPC classification number: G06F1/26 ,  G06F1/00 ,  G06F1/3253 ,  G06F11/0706 ,  G06F11/0754 ,  G06F11/0793 ,  Y02D10/151

    Abstract: Methods and apparatus related to adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications are described. In some embodiments, a first bit pattern is detected, at a first agent, that indicates a speculative entry by a second agent into a low power consumption state and one or more control loops are frozen. A second bit pattern is detected (after entering the low power consumption state) that indicates exit from the low power consumption state by the second agent and the one or more control loops are unfrozen (e.g., in a specific order). Other embodiments are also claimed and/or disclosed.

    Abstract translation: 描述了与高速串行I / O应用中的低功率状态快速稳健恢复的自适应控制回路保护相关的方法和设备。 在一些实施例中，在第一代理处检测到第一位模式，其指示由第二代理进入低功耗状态的推测输入，并且一个或多个控制回路被冻结。 检测到第二位模式（在进入低功耗状态之后），其指示由第二代理从低功耗状态退出并且一个或多个控制回路被解冻（例如，以特定顺序）。 还要求和/或公开其它实施例。

    UNEQUALIZED CLOCK DATA RECOVERY FOR SERIAL I/O RECEIVER
    2.
    发明申请
    UNEQUALIZED CLOCK DATA RECOVERY FOR SERIAL I/O RECEIVER 审中-公开
    用于串行I / O接收器的不平衡时钟数据恢复

    公开(公告)号：US20170070370A1

    公开(公告)日：2017-03-09

    申请号：US15332376

    申请日：2016-10-24

    Applicant: Intel Corporation

    Inventor： Yun He ,  Sanjib Sarkar ,  Fei Deng ,  Senthil Arun Singaravelu ,  Narender Nagulapally ,  Pranali Shah

    IPC: H04L25/03 ,  H04L7/00 ,  H04L7/033

    CPC classification number: H04L25/03057 ,  G06F13/4072 ,  H04L7/0062 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/0276 ,  H04L7/033 ,  H04L7/0332 ,  H04L25/03949

    Abstract: A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.

    Abstract translation: 串行输入/输出方法和接收器包括接收模拟差分串行输入并对输入进行采样以提供数据和误差信号的接收器部分，响应于数据和误差信号的均衡反馈回路以调整接收器部分，相位反馈 与均衡反馈环路分离以提供相位误差，以及时钟数据恢复块，其耦合以接收相位误差，以独立于均衡反馈来执行接收器部分的定时恢复以调整采样。

    ADAPTIVE BACKCHANNEL EQUALIZATION
    3.
    发明申请
    ADAPTIVE BACKCHANNEL EQUALIZATION 审中-公开
    自适应反向信道均衡

    公开(公告)号：US20160080179A1

    公开(公告)日：2016-03-17

    申请号：US14859339

    申请日：2015-09-20

    Applicant: Intel Corporation

    Inventor： Yun He ,  Sanjib Sarkar

    IPC: H04L25/03

    CPC classification number: H04L25/03878 ,  H04L25/03343

    Abstract: Techniques for adaptive backchannel equalization. A total equalization value is determined over a preselected training period. A total balance equalization value is determined over the preselected training period. A transmitter equalization coefficient is determined based on the total equalization value and the total balance equalization value. Data is transmitted over a serial link using the transmitter equalization coefficient.

    Abstract translation: 自适应反向信道均衡技术。 在预选的训练期间确定总均衡值。 在预选的训练期间确定总平衡均衡值。 基于总均衡值和总平衡均衡值来确定发射机均衡系数。 使用发射机均衡系数通过串行链路传输数据。

    Adaptive backchannel equalization
    4.
    发明授权
    Adaptive backchannel equalization 有权
    自适应反向信道均衡

    公开(公告)号：US09143369B2

    公开(公告)日：2015-09-22

    申请号：US13897947

    申请日：2013-05-20

    Applicant: INTEL CORPORATION

    Inventor： Yun He ,  Sanjib Sarkar

    IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03

    CPC classification number: H04L25/03878 ,  H04L25/03343

    Abstract: Techniques for adaptive backchannel equalization. A total equalization value is determined over a preselected training period. A total balance equalization value is determined over the preselected training period. A transmitter equalization coefficient is determined based on the total equalization value and the total balance equalization value. Data is transmitted over a serial link using the transmitter equalization coefficient.

    Abstract translation: 自适应反向信道均衡技术。 在预选的训练期间确定总均衡值。 在预选的训练期间确定总平衡均衡值。 基于总均衡值和总平衡均衡值来确定发射机均衡系数。 使用发射机均衡系数通过串行链路传输数据。

    Jitter sensing and adaptive control of parameters of clock and data recovery circuits
    6.
    发明授权
    Jitter sensing and adaptive control of parameters of clock and data recovery circuits 有权

    公开(公告)号：US10237051B2

    公开(公告)日：2019-03-19

    申请号：US15979219

    申请日：2018-05-14

    Applicant: Intel Corporation

    Inventor： Yun He ,  Adhiveeraraghavan Srikanth ,  Sanjib Sarkar

    IPC: H04L7/027 ,  H04L7/00 ,  H04L7/033

    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for jitter sensing and adaptive control of parameters of clock and data recovery (CDR) circuits. A receiver component includes an adaptive CDR loop dynamic control circuit. The adaptive CDR loop dynamic control circuit is to detect first sinusoidal jitter at a first frequency and a first amplitude and update parameters of the CDR circuit to a first plurality of values based on the first frequency and the first amplitude. The adaptive CDR loop dynamic control circuit is further to detect second sinusoidal jitter at a second frequency and a second amplitude and update the parameters of the CDR circuit to a second plurality of values based on the second frequency and the second amplitude. The first sinusoidal jitter is in a first incoming data signal and the second sinusoidal jitter is in a second incoming data signal.

    Adaptive backchannel equalization
    7.
    发明授权
    Adaptive backchannel equalization 有权

    公开(公告)号：US09521021B2

    公开(公告)日：2016-12-13

    申请号：US14859339

    申请日：2015-09-20

    Applicant: Intel Corporation

    Inventor： Yun He ,  Sanjib Sarkar

    IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03

    CPC classification number: H04L25/03878 ,  H04L25/03343

    Abstract: Techniques for adaptive backchannel equalization. A total equalization value is determined over a preselected training period. A total balance equalization value is determined over the preselected training period. A transmitter equalization coefficient is determined based on the total equalization value and the total balance equalization value. Data is transmitted over a serial link using the transmitter equalization coefficient.

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