公开(公告)号：US20240105801A1

公开(公告)日：2024-03-28

申请号：US17951974

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sukru YEMENICIOGLU ,  Raghuram GANDIKOTA ,  Krishna GANESAN ,  Sean PURSEL

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/775 ,  H01L2029/42388

Abstract: Integrated circuit structures having gate volume reduction, and methods of fabricating integrated circuit structures having gate volume reduction, are described. For example, an integrated circuit structure includes a sub-fin structure beneath a stack of nanowires, the stack of nanowires having a first side and a second side. A dielectric backbone structure is along the first side of the stack of nanowires. The dielectric backbone structure has a bottom above a bottom of the sub-fin. A gate electrode is over the stack of nanowires and is along the second side of the stack of nanowires. A gate dielectric structure is between the gate electrode and the stack of nanowires.