公开(公告)号：US20160087805A1

公开(公告)日：2016-03-24

申请号：US14490402

申请日：2014-09-18

Applicant: Intel Corporation

Inventor： JIANGTAO LI ,  WEI WU ,  PATRICK KOEBERL

IPC: H04L9/32 ,  G06F11/07 ,  H04L9/06

CPC classification number: H04L9/3278 ,  H04L9/0866

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing a post-processing mechanism for physically unclonable functions. An integrated circuit includes a physically unclonable function (PUF) unit including an adaptive PUF logic. The adaptive PUF logic receives a PUF response having a plurality of bits. The adaptive PUF logic also determines whether a record exists for bit among the plurality of bits in the PUF response. The record includes a stored bit location and a stored bit value corresponding to the stored bit location. The adaptive PUF logic also overrides a bit value of the bit in the PUF response with the stored bit value when it is determined that the record exists for the bit in the PUF response. The bit value of the bit in the PUF response is different from the stored bit value.

Abstract translation: 根据本文公开的实施例，提供了用于提供用于物理不可克隆功能的后处理机构的系统和方法。 集成电路包括包括自适应PUF逻辑的物理不可克隆功能（PUF）单元。 自适应PUF逻辑接收具有多个比特的PUF响应。 自适应PUF逻辑还确定在PUF响应中的多个比特中是否存在针对比特的记录。 记录包括存储的比特位置和对应于存储的比特位置的存储的比特值。 当确定在PUF响应中存在该比特的记录时，自适应PUF逻辑还用存储的比特值来覆盖PUF响应中的比特的比特值。 PUF响应中的位的位值与存储的位值不同。

公开(公告)号：US20190220349A1

公开(公告)日：2019-07-18

申请号：US16368430

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： SERGEJ DEUTSCH ,  WEI WU ,  DAVID M. DURHAM ,  KARANVIR GREWAL

IPC: G06F11/10 ,  H04L9/32

Abstract: In one example a computer implemented method comprises generating an error correction code for a memory line, the memory line comprising a first plurality of data blocks, wherein the error correction code comprises a first plurality of parity bits and a second plurality of parity bits, applying a domain-specific function to the second plurality of parity bits to generate a modified block of parity bits, generating a metadata block corresponding to the memory line, wherein the metadata block comprises the error correction code for the memory line and at least a portion of the modified block of parity bits, encoding the first plurality of data blocks and the metadata block to generate a first encoded data set, and providing the encoded data set and the encoded metadata block for storage on a memory module. Other examples may be described.

公开(公告)号：US20160379700A1

公开(公告)日：2016-12-29

申请号：US14751801

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： CHARLES AUGUSTINE ,  SHIGEKI TOMISHIMA ,  WEI WU ,  SHIH-LIEN LU ,  JAMES W. TSCHANZ ,  GEORGIOS PANAGOPOULOS ,  HELIA NAEIMI

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/1697

Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

Abstract translation: 描述了一种包括具有电阻存储单元的半导体芯片存储器阵列的装置。 该装置还包括比较器，用于将写入阵列的第一个字与存储在阵列中的第二个字进行比较，该第二个字由写入操作所指向的位置将第一个字写入数组。 该装置还包括用于迭代地写入一个或多个比特位置的电路​​，其中在每个连续的迭代中随着写入电流强度的增加而在第一个字和第二个字之间存在差异。