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    Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA)
    3.
    发明授权
    Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA) 有权

    公开(公告)号：US12277060B2

    公开(公告)日：2025-04-15

    申请号：US17334700

    申请日：2021-05-29

    Applicant: Intel Corporation

    Inventor： Sailesh Kumar

    IPC: G06F12/0813 ,  G06F9/38 ,  G06F12/0811 ,  G06F15/78 ,  G06F30/331 ,  H04L45/302 ,  H04L45/586 ,  H04L45/60 ,  H04L49/109

    Abstract: Methods and example implementations described herein are generally directed to the addition of networks-on-chip (NoC) to FPGAs to customize traffic and optimize performance. An aspect of the present application relates to a Field-Programmable Gate-Array (FPGA) system. The FPGA system can include an FPGA having one or more lookup tables (LUTs) and wires, and a Network-on-Chip (NoC) having a hardened network topology configured to provide connectivity at a higher frequency that the FPGA. The NoC is coupled to the FPGA to receive an profile information associated with an application, retrieve at least a characteristic, selected form any of combination of any or combination of a bandwidth requirement, latency requirement, protocol requirement and transactions, associated with the application from the profile information, generate at least one application traffic graph having mapping information based on the characteristic retrieved, and map the application traffic graph generated with into the FPGA using the hardened NoC.

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