公开(公告)号：US20230350829A1

公开(公告)日：2023-11-02

申请号：US18349055

申请日：2023-07-07

Applicant: Intel Corporation

Inventor： Swadesh Choudhary ,  Robert G. Blankenship ,  Siva Prasad Gadey ,  Sailesh Kumar ,  Vinit Mathew Abraham ,  Yen-Cheng Liu

IPC: G06F13/40

CPC classification number: G06F13/4027

Abstract: An interface for coupling an agent to a fabric supports a set of coherent interconnect protocols and includes a global channel to communicate control signals to support the interface, a request channel to communicate messages associated with requests to other agents on the fabric, a response channel to communicate responses to other agents on the fabric, and a data channel to couple to communicate messages associated with data transfers to other agents on the fabric, where the data transfers include payload data.

公开(公告)号：US11698879B2

公开(公告)日：2023-07-11

申请号：US16914327

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Swadesh Choudhary ,  Robert G. Blankenship ,  Siva Prasad Gadey ,  Sailesh Kumar ,  Vinit Mathew Abraham ,  Yen-Cheng Liu

IPC: G06F13/40

CPC classification number: G06F13/4027

Abstract: An interface for coupling an agent to a fabric supports a set of coherent interconnect protocols and includes a global channel to communicate control signals to support the interface, a request channel to communicate messages associated with requests to other agents on the fabric, a response channel to communicate responses to other agents on the fabric, and a data channel to couple to communicate messages associated with data transfers to other agents on the fabric, where the data transfers include payload data.

公开(公告)号：US09785223B2

公开(公告)日：2017-10-10

申请号：US14583151

申请日：2014-12-25

Applicant: Intel Corporation

Inventor： Ramadass Nagarajan ,  Jeremy J. Shrall ,  Erik G. Hallnor ,  Vinit Mathew Abraham ,  Ezra N. Harrington

IPC: G06F1/32 ,  G06F1/28

CPC classification number: G06F1/3287 ,  G06F1/28 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3253 ,  Y02D10/171

Abstract: In an example, a shared uncore memory fabric of a system-on-a-chip (SoC) is configured to provide real-time power management. The SoC may include a power management agent to inform the shared fabric that the processing cores and peripherals will be idle for a time, and to negotiate a power-saving state. The uncore fabric may also include a local power manager that detects when no access requests have been received for a time, such as when cores are operating from cache. The shared fabric may then unilaterally enter a power-saving state, and remain in that state until an access request is received. In the power-saving state, power and/or clocks are gated, and the fabric's state is stored in retention cells. When a new access request is received, an ungated controller may handle preliminary processing while the local power manager restores the state and powers up the shared fabric.

公开(公告)号：US20250103397A1

公开(公告)日：2025-03-27

申请号：US18401399

申请日：2023-12-30

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Daniel Joe ,  Filip Schmole ,  Philip Abraham ,  Stephen R. Van Doren ,  Priya Autee ,  Rajesh M. Sankaran ,  Anthony Luck ,  Philip Lantz ,  Eric Wehage ,  Edwin Verplanke ,  James Coleman ,  Scott Oehrlein ,  David M. Lee ,  Lee Albion ,  David Harriman ,  Vinit Mathew Abraham ,  Yi-Feng Liu ,  Manjula Peddireddy ,  Robert G. Blankenship

IPC: G06F9/50

Abstract: Techniques for quality of service (QoS) support for input/output devices and other agents are described. In embodiments, a processing device includes execution circuitry to execute a plurality of software threads; hardware to control monitoring or allocating, among the plurality of software threads, one or more shared resources; and configuration storage to enable the monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more channels through which one or more devices are to be connected to the one or more shared resources.

公开(公告)号：US12261936B2

公开(公告)日：2025-03-25

申请号：US17213465

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Vinit Mathew Abraham ,  Raghunandan Makaram ,  Kirk S. Yap ,  Siva Prasad Gadey ,  Tanmoy Kar

IPC: G06F21/62 ,  G06F16/23 ,  H04L9/06 ,  H04L9/08

Abstract: Techniques for real-time updating of encryption keys are disclosed. In the illustrative embodiment, an encrypted link is established between a local and remote processor over a point-to-point interconnect. The encrypted link is operated for some time until the encryption key should be updated. The local processor sends a key update message to the remote processor notifying the remote processor of the change. The remote processor prepares for the change and sends a key update confirmation message to the local processor. The local processor then sends a key switch message to the remote processor. The local processor pauses transmission of encrypted message while the remote processor completes use of the encrypted message. After a pause, the local processor continues sending encrypted messages with the updated encryption key.

公开(公告)号：US20210218548A1

公开(公告)日：2021-07-15

申请号：US17213465

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Vinit Mathew Abraham ,  Raghunandan Makaram ,  Kirk S. Yap ,  Siva Prasad Gadey ,  Tanmoy Kar

IPC: H04L9/06 ,  H04L9/08

Abstract: Techniques for real-time updating of encryption keys are disclosed. In the illustrative embodiment, an encrypted link is established between a local and remote processor over a point-to-point interconnect. The encrypted link is operated for some time until the encryption key should be updated. The local processor sends a key update message to the remote processor notifying the remote processor of the change. The remote processor prepares for the change and sends a key update confirmation message to the local processor. The local processor then sends a key switch message to the remote processor. The local processor pauses transmission of encrypted message while the remote processor completes use of the encrypted message. After a pause, the local processor continues sending encrypted messages with the updated encryption key.

公开(公告)号：US12271760B2

公开(公告)日：2025-04-08

申请号：US17477470

申请日：2021-09-16

Applicant: Intel Corporation

Inventor： Vinit Mathew Abraham ,  Anand K. Enamandram ,  Eswaramoorthi Nallusamy

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/4401 ,  G06F13/42

Abstract: A first plurality of integrated circuit blocks of a first chip are connected to a second plurality of integrated circuit blocks of a second chip. A cluster remapping table is provided on the second chip and is to be programmed to identify a desired asymmetric topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks. Logic is to discover the actual topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks and determine whether the actual topology matches the desired topology as described in the cluster remapping table.

公开(公告)号：US12253947B2

公开(公告)日：2025-03-18

申请号：US17223994

申请日：2021-04-06

Applicant: Intel Corporation

Inventor： Vinit Mathew Abraham ,  Yen-Cheng Liu

IPC: G06F12/00 ,  G06F12/0815

Abstract: Examples described herein relate to programming a memory rule for a home agent, wherein the programming a memory rule for a home agent comprises: receiving at least one memory rule programming and based on a cluster associated with the home agent, configuring a memory rule register using a memory rule programming from among the at least one memory rule programming. In some examples, receiving at least one memory rule programming includes receiving a first memory rule programming and receiving a second memory rule programming. In some examples, a mask is applied to reject the first memory rule programming; and applying the mask to accept the second memory rule programming and program the memory rule for the home agent.

公开(公告)号：US12111783B2

公开(公告)日：2024-10-08

申请号：US18349055

申请日：2023-07-07

Applicant: Intel Corporation

Inventor： Swadesh Choudhary ,  Robert G. Blankenship ,  Siva Prasad Gadey ,  Sailesh Kumar ,  Vinit Mathew Abraham ,  Yen-Cheng Liu

IPC: G06F13/40

CPC classification number: G06F13/4027

Abstract: An interface for coupling an agent to a fabric supports a set of coherent interconnect protocols and includes a global channel to communicate control signals to support the interface, a request channel to communicate messages associated with requests to other agents on the fabric, a response channel to communicate responses to other agents on the fabric, and a data channel to couple to communicate messages associated with data transfers to other agents on the fabric, where the data transfers include payload data.

公开(公告)号：US11966330B2

公开(公告)日：2024-04-23

申请号：US16894402

申请日：2020-06-05

Applicant: Intel Corporation

Inventor： Vinit Mathew Abraham ,  Jeffrey D. Chamberlain ,  Yen-Cheng Liu ,  Eswaramoorthi Nallusamy ,  Soumya S. Eachempati

IPC: G06F13/16 ,  G06F12/08 ,  G06F12/0802 ,  G06F13/40

CPC classification number: G06F12/0802 ,  G06F13/1668 ,  G06F13/4027 ,  G06F2213/16 ,  G06F2213/40

Abstract: Examples described herein relate to processor circuitry to issue a cache coherence message to a central processing unit (CPU) cluster by selection of a target cluster and issuance of the request to the target cluster, wherein the target cluster comprises the cluster or the target cluster is directly connected to the cluster. In some examples, the selected target cluster is associated with a minimum number of die boundary traversals. In some examples, the processor circuitry is to read an address range for the cluster to identify the target cluster using a single range check over memory regions including local and remote clusters. In some examples, issuance of the cache coherence message to a cluster is to cause the cache coherence message to traverse one or more die interconnections to reach the target cluster.